TECHNICAL DATA
Octal D-type transparent latch (3-State)
The 74LV573 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT573.
The 74LV573 is an octal D-type transparent latch featuring separate D-
type inputs for each latch and 3-State outputs for bus oriented applications.
A latch enable (LE) input and an output enable (OE) input are common to
all internal latches.
The ‘573’ consists of eight D-type transparent latches with 3-State true
outputs. When LE is HIGH, data at the D n inputs enters the latches. In this
condition the latches are transparent, i.e., a latch output will change each
time its corresponding D-input changes.
When LE is LOW the latches store the information that was present at
the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE.
When OE is LOW, the contents of the eight latches are available at the
outputs. When OE is HIGH, the outputs go to the high impedance OFF-
state. Operation of the OE input does not affect the state of the latches.
The ‘573’ is functionally identical to the ‘563’ and the ‘373’, but the
‘563’ has inverted outputs and the ‘373’ has a different pin arrangement.
•
Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL IC
S
•
Supply voltage range: 1.0 to 5.5 V
•
Low input current: 1.0
µА;
0.1
µА
at
Т
= 25
°С
•
High Noise Immunity Characteristic of CMOS Devices
IN74LV573
N SUFFIX
PLASTIC DIP
20
1
20
1
DW SUFFIX
SO
ORDERING INFORMATION
IN74LV573N
Plastic DIP
IN74LV573DW
SOIC
T
A
= -40° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Output
Enable
L
L
PIN 20=V
CC
PIN 10 = GND
L
H
L,H,
X
Clock
D
H
L
X
X
Output
Q
H
L
no
change
Z
H= high level
L = low level
X = don’t care
Z = high impedance
1
IN74LV573
MAXIMUM RATINGS
*
Symbol
V
CC
I
IK
*
1
I
OK
*
2
I
O
*
3
I
CC
I
GND
P
D
DC supply voltage
Input diode current
Output diode current
Output source or sink current
V
CC
current
GND current
Power dissipation per package:
Plastic DIP *
4
SO *
4
Storage Temperature
Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm
(SO Package) from Case for 4 Seconds
Parameter
Value
-0.5 to +7.0
±20
±50
±35
±70
±50
750
500
-65 to +150
260
°C
°C
Unit
V
mA
mA
mA
mA
mA
mW
Tstg
T
L
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
*
1
V
I
< -0.5 V or V
I
> V
CC
+ 0.5 V.
*
2
V
O
< -0.5 V or V
O
> V
CC
+ 0.5 V.
*
3
-0.5 V < V
O
< V
CC
+ 0.5 V.
*
4
Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C
SO Package: - 8 mW/°C from 70° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
V
O
T
A
t
r
, t
f
DC Supply Voltage
DC Input Voltage
DC Output Voltage
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
0 V
≤
V
CC
≤
2.0 V
2.0 V
≤
V
CC
≤
2.7 V
2.7 V
≤
V
CC
≤
3.6 V
3.6 V
≤
V
CC
≤
5.5 V
Parameter
Min
1.2
0
0
-40
0
0
0
0
Max
5.5
V
CC
V
CC
+125
500
200
100
50
Unit
V
V
V
°C
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range GND≤(V
IN
or
V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
2
IN74LV573
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Test
Symbol
V
IH
Parameter
HIGH level
input
voltage
conditions
V
CC
V
1.2
2.0
2.7
3.0
3.6
4.5
5.5
1.2
2.0
2.7
3.0
3.6
4.5
5.5
1.2
2.0
2.7
3.0
3.6
4.5
5.5
3.0
4.5
1.2
2.0
2.7
3.0
3.6
4.5
5.5
3.0
4.5
5.5
5.5
2.7
3.6
25°C
min
0.9
1.4
2.0
2.0
2.0
3.15
3.85
-
-
-
-
-
-
-
1.05
1.85
2.55
2.85
3.45
4.35
5.35
2.48
3.70
-
-
-
-
-
-
-
-
-
-
-
-
max
-
-
-
-
-
-
-
0.3
0.6
0.8
0.8
0.8
1.35
1.65
-
-
-
-
-
-
-
-
-
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.33
0.40
±0.1
8.0
0.2
min
0.9
1.4
2.0
2.0
2.0
3.15
3.85
-
-
-
-
-
-
-
1.05
1.85
2.55
2.85
3.45
4.35
5.35
2.48
3.70
-
-
-
-
-
-
-
-
-
-
-
-
Guaranteed Limit
-40°C
max
-
-
-
-
-
-
-
0.3
0.6
0.8
0.8
0.8
1.35
1.65
-
-
-
-
-
-
-
-
-
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.33
0.40
±0.1
8.0
0.2
min
0.9
1.4
2.0
2.0
2.0
3.15
3.85
-
-
-
-
-
-
-
1.0
1.8
2.5
2.8
3.4
4.3
5.3
2.40
3.60
-
-
-
-
-
-
-
-
-
-
-
-
85°C
max
-
-
-
-
-
-
-
0.3
0.6
0.8
0.8
0.8
1.35
1.65
-
-
-
-
-
-
-
-
-
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.40
0.55
±1.0
80
0.5
125°C
min
0.9
1.4
2.0
2.0
2.0
3.15
3.85
-
-
-
-
-
-
-
1.0
1.8
2.5
2.8
3.4
4.3
5.3
2.20
3.50
-
-
-
-
-
-
-
-
-
-
-
max
-
-
-
-
-
-
-
0.3
0.6
0.8
0.8
0.8
1.35
1.65
-
-
-
-
-
-
-
-
-
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.50
0.65
±1.0
160
0.85
V
Unit
V
IL
LOW level
output
voltage
V
V
OH
HIGH level V
I
= V
IH
or V
IL
output
I
O
= -100
µА
voltage
V
V
I
= V
IH
or V
IL
I
O
= -8 mА
V
I
= V
IH
or V
IL
I
O
= -16 mА
V
OL
LOW level
output
voltage
V
I
= V
IH
or V
IL
I
O
= 100
µА
V
V
V
V
I
= V
IH
or V
IL
I
O
= 8 mА
V
I
= V
IH
or V
IL
I
O
= 16 mА
I
I
I
CC
I
CC1
Input
current
Supply
current
Additional
supply
current per
input
Three state
leakage
current
V
I
= V
CC
or 0 V
V
I
=V
CC
or 0 V
I
O
= 0
µА
V
I
= V
CC
–
0.6V
V
V
µА
µА
mA
I
OZ
3-state output
V
I
(11) = V
IH
V
O
=V
CC
or 0 V
5.5
-
±0.5
-
±0.5
-
±5
-
±10
µА
3
IN74LV573
AC ELECTRICAL CHARACTERISTICS
(C
L
=50 pF, t
r
=t
f
=2.5 ns)
Test
Symbol
Parameter
conditions
V
I
= 0 V or V
1
Figures 1,3
V
CC
V
1.2
2.0
2.7
3.0
4.5
1.2
2.0
2.7
3.0
4.5
1.2
2.0
2.7
3.0
4.5
1.2
2.0
2.7
3.0
4.5
5.0
V
I
= 0 V or V
CC
5.5
min
t
PHL,
t
PLH
Propagation delay , Clock
to Q
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
max
150
30
23
18
15
160
34
28
20
17
160
31
23
20
17
140
28
22
17
14
7.0*
52*
Guaranteed Limit
-40°C to 25°C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
85°C
min
max
160
39
29
23
19
180
43
31
25
21
160
39
29
24
20
160
37
28
22
18
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
125°C
min
max
170
49
36
29
24
190
53
34
31
26
170
48
36
29
24
170
48
35
28
23
-
-
ns
Unit
t
PHL,
t
PLH
Propagation delay , LE to
Q
V
I
= 0 V or V
1
Figures 1,3
ns
t
PHZ,
t
PLZ
Propagation delay, OE to
Q
V
I
= 0 V or V
1
Figures 2,4
ns
t
PZH,
t
PZL
Propagation delay, OE to
Q
V
I
= 0 V or V
1
Figures 2,4
ns
C
I
C
PD
Input capacitance
Power dissipation
capacitance (
per latch
)
pF
pF
* T = 25
o
C
4
IN74LV573
TIMING REQUIREMENTS
(C
L
=50 pF, t
r
=t
f
=2.5 ns)
Test
Symbol
t
w
Parameter
Pulse Width, LE (low or
high)
conditions
V
I
= 0 V or V
1
Figures 1,3
V
CC
V
1.2
2.0
2.7
3.0
4.5
1.2
2.0
2.7
3.0
4.5
1.2
2.0
2.7
3.0
4.5
min
100
29
21
17
15
50
15
11
8
6
40
8
8
8
8
max
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Guaranteed Limit
-40°C to 25°C
125
34
25
20
18
75
17
13
10
8
40
8
8
8
8
85°C
min
max
-
-
-
-
-
-
-
-
-
-
-
-
125°C
min
150
41
30
24
21
100
20
15
12
10
40
8
8
8
8
max
ns
-
-
-
-
ns
-
-
-
-
-
-
-
-
ns
Unit
t
su
Setup Time, Data to LE
V
I
= 0 V or V
1
Figures 1,5
t
h
Hold Time, LE to Data
V
I
= 0 V or V
1
Figures 1,5
TEST POINT
DEVICE
UNDER
TEST
TEST POINT
1k
C
L
*
OUTPUT
C
L
*
DEVICE
UNDER
TEST
OUTPUT
Connect to V
CC
when
testing t
PLZ
and t
PZL
Connect to GND when
testing t
PHZ
and t
PZH
* Includes all probe and jig capacitance
Figure 1. Test Circuit
* Includes all probe and jig capacitance
Figure 2. Test Circuit
Figure 3. Switching Waveforms
5
DSP 与 ARM 处理器
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
