TECHNICAL DATA
IN74ACT299
8-Bit Bidirectional Universal
Shift Register with Parallel I/O
High-Speed Silicon-Gate CMOS
The IN74ACT299 is identical in pinout to the LS/ALS299,
HC/HCT299. The IN74ACT299 may be used as a level converter for
interfacing TTL or NMOS outputs to High Speed CMOS inputs.
The IN74ACT299 features a multiplexed parallel input/output data
port to achieve full 8-bit handling in a 20 pin package. Due to the large
output drive capability and the 3-state feature, this device is ideally suited
for interface with bus lines in a bus-oriented system.
Two Mode-Select inputs and two Output Enable inputs are used to
choose the mode of operation as listed in the Function Table.
Synchronous parallel loading is accomplished by taking both Mode-
Select lines, S
1
and S
2
, high. This places the outputs in the high-
impedance state, which permits data applied to the data port to be clocked
into the register. Reading out of the register can be accomplished when
the outputs are enabled. The active-low asynchronous Reset overrides all
other inputs.
•
TTL/NMOS Compatible Input Levels
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 4.5 to 5.5 V
•
Low Input Current: 1.0
µA;
0.1
µA
@ 25°C
•
Outputs Source/Sink 24 mA
ORDERING INFORMATION
IN74ACT299N Plastic
IN74ACT299DW SOIC
T
A
= -40° to 85° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 20=V
CC
PIN 10 = GND
Rev. 00
IN74ACT299
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
I
CC
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Sink/Source Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +7.0
-0.5 to V
CC
+0.5
-0.5 to V
CC
+0.5
±20
±50
±50
750
500
-65 to +150
260
Unit
V
V
V
mA
mA
mA
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
J
T
A
I
OH
I
OL
t
r
, t
f
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Junction Temperature (PDIP)
Operating Temperature, All Package Types
Output Current - High
Output Current - Low
Input Rise and Fall Time
*
(except Schmitt Inputs)
V
CC
=4.5 V
V
CC
=5.5 V
Min
4.5
0
-40
Max
5.5
V
CC
140
+85
-24
24
Unit
V
V
°C
°C
mA
mA
ns/V
0
0
10
8.0
V
IN
from 0.8 V to 2.0 V
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range GND≤(V
IN
or
V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
Rev. 00
IN74ACT299
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum High-
Level Input Voltage
Maximum Low -
Level Input Voltage
Minimum High-
Level Output Voltage
Test Conditions
V
OUT
= 0.1 V or V
CC
-0.1 V
V
OUT
= 0.1 V or V
CC
-0.1 V
I
OUT
≤
-50
µA
V
IN
=V
IH
or V
IL
I
OH
=-24 mA
I
OH
=-24 mA
V
OL
Maximum Low-
Level Output Voltage
I
OUT
≤
50
µA
*
*
Guaranteed Limits
25
°C
2.0
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.1
0.1
0.36
0.36
±0.1
-40°C to
85°C
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
±1.0
1.5
±0.6
±6.0
µA
mA
µA
V
Unit
V
V
V
V
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
5.5
5.5
5.5
V
IN
= V
IH
or V
IL
I
OL
=24 mA
I
OL
=24 mA
V
IN
=V
CC
or GND
V
IN
=V
CC
- 2.1 V
I
IN
∆I
CCT
I
OZ
Maximum Input
Leakage Current
Additional Max.
I
CC
/Input
Maximum Three-
State Leakage
Current
+Minimum Dynamic
Output Current
+Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
(per Package)
V
IN
(OE)= V
IH
or V
IL
V
IN
=V
CC
or GND
V
OUT
=V
CC
or GND
V
OLD
=1.65 V Max
V
OHD
=3.85 V Min
V
IN
=V
CC
or GND
I
OLD
I
OHD
I
CC
5.5
5.5
5.5
8.0
75
-75
80
mA
mA
µA
*
All outputs loaded; thresholds on input associated with output under test.
+Maximum test duration 2.0 ms, one output loaded at a time.
Rev. 00
IN74ACT299
AC ELECTRICAL CHARACTERISTICS
(V
CC
=5.0 V
±
10%, C
L
=50pF,Input t
r
=t
f
=3.0 ns)
Guaranteed Limits
Symbol
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
C
IN
Parameter
Maximum Clock Frequency (Figure 1)
Propagation Delay, Clock to Q
A
’ or Q
H
’ (Figure 1)
Propagation Delay, Clock to Q
A
’ or Q
H
’ (Figure 1)
Propagation Delay, Clock to Q
A
thru Q
H
(Figure 1)
Propagation Delay, Clock to Q
A
thru Q
H
(Figure 1)
Propagation Delay, Reset to Q
A
’ or Q
H
’ (Figure 2)
Propagation Delay, Reset to Q
A
thru Q
H
(Figure 2)
Propagation Delay , OE1, OE2 to Q
A
thru Q
H
(Figure 3)
Propagation Delay , OE1, OE2 to Q
A
thru Q
H
(Figure 3)
Propagation Delay , OE1, OE2 to Q
A
thru Q
H
(Figure 3)
Propagation Delay , OE1, OE2 to Q
A
thru Q
H
(Figure 3)
Maximum Input Capacitance
25
°C
Min
120
4.0
4.0
4.5
5.0
4.0
4.0
2.5
2.0
2.0
2.5
4.5
12.5
13.5
12.5
15.0
15.0
14.5
12.0
12.0
12.5
11.5
Max
-40°C to 85°C
Min
110
3.0
3.5
4.5
4.5
4.0
3.5
1.5
1.5
2.0
2.0
4.5
14.0
15.0
13.5
16.5
18.0
17.5
13.0
13.5
13.5
12.5
Max
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
Unit
Typical @25°C,V
CC
=5.0 V
C
PD
Power Dissipation Capacitance
170
pF
TIMING REQUIREMENTS
(V
CC
=5.0 V
±
10%, C
L
=50pF, Input t
r
=t
f
=3.0 ns)
Guaranteed Limits
Symbol
t
su
t
su
t
su
t
h
t
h
t
h
t
rec
t
w
t
w
Parameter
Minimum Setup Time, Mode Select S1 or S2 to Clock (Figure 4)
Minimum Setup Time, Data Inputs P
A
thru P
H
to Clock (Figure 4)
Minimum Setup Time, Data Inputs S
A
, S
H
to Clock (Figure 4)
Minimum Hold Time, Clock to Mode Select S1 or S2 (Figure 4)
Minimum Hold Time, Clock to Data Inputs P
A
thru P
H
(Figure 4)
Minimum Hold Time, Clock to Data Inputs S
A
, S
H
(Figure 4)
Minimum Recovery Time, Reset Inactive to Clock (Figure 2)
Minimum Pulse Width, Clock (Figure 1)
Minimum Pulse Width, Reset (Figure 2)
25
°C
5.0
4.0
4.5
1.0
1.0
1.0
1.5
4.0
3.5
-40°C to
85°C
5.5
4.5
5.0
1.0
1.0
1.0
1.5
4.5
3.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. 00
IN74ACT299
FUNCTION TABLE
Inputs
Mode
Reset
Mode
Select
S
2
Reset
L
L
L
Shift
Right
H
H
H
Shift
Left
H
H
H
Parallel
Load
Hold
H
H
H
H
X
L
H
L
L
L
H
H
H
H
L
L
L
S
1
L
X
H
H
H
H
L
L
L
H
L
L
L
Output
Enables
OE1
L
L
X
H
X
L
H
X
L
X
H
X
L
OE2
L
L
X
X
H
L
X
H
L
X
X
H
L
X
X
X
X
X
X
Clock
Serial
Inputs
D
A
D
H
X
X
X
D
D
D
X
X
X
X
X
X
X
X
X
X
X
X
X
D
D
D
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
D
D
D
Q
B
Q
B
Q
B
P
A
P
A
P
A
P
A
L
L
L
Q
G
Q
G
Q
G
D
D
D
P
H
P
H
P
H
P
H
Response
P
A
/ P
B
/ P
C
/ P
D
/ P
E
/ P
F
/ P
G
/ P
H
/ Q
A
’ Q
H
’
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
Q
A
through Q
H
=Z
Shift Right: Q
A
through Q
H
=Z;
F
A
; F
A
F
B
; etc
D
A
Shift Right: Q
A
through Q
H
=Z;
F
A
; F
A
F
B
; etc
D
A
Shift Right: D
A
F
A
=Q
A
;
F
B
=Q
B
; etc
F
A
Shift Left: Q
A
through Q
H
=Z;
F
H
; F
H
F
G
; etc
D
H
Shift Left: Q
A
through Q
H
=Z;
F
H
; F
H
F
G
; etc
D
H
Shift Left: D
H
F
H
=Q
H
;
F
G
=Q
G
; etc
F
H
Parallel Load:P
N
F
N
Hold: Q
A
through Q
H
=Z; F
N
=F
N
Hold: Q
A
through Q
H
=Z; F
N
=F
N
Hold: Q
N
=Q
H
Z = high impedance
D = data on serial input
F = flip-flop (see Logic Diagram)
When one or both output controls are high the eight input/output terminals are disabled to the high-
impedance state; however, sequential operation or clearing of the register is not affected.
Rev. 00
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
