TECHNICAL DATA
IN74AC651
Octal 3-State Bus Transceivers
and D Flip-Flops
High-Speed Silicon-Gate CMOS
The IN74AC651 is identical in pinout to the LS/ALS651,
HC/HCT651. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LS/ALS outputs.
These devices consists of bus transceiver circuits, D-type flip-flop,
and control circuitry arranged for multiplex transmission of data directly
from the data bus or from the internal storage registers. Direction and
Output Enable are provided to select the read-time or stored data function.
Data on the A or B Data bus, or both, can be stored in the internal D flip-
flops by low-to-high transitions at the appropriate clock pins (A-to-B
Clock or B-to-A Clock) regardless of the select or enable or enable
control pins. When A-to-B Source and B-to-A Source are in the real-time
transfer mode, it is also possible to store data without using the internal
D-type flip-flops by simultaneously enabling Direction and Output
Enable. In this configuration each output reinforces its input. Thus, when
all other data sources to the two sets of bus lines are at high impedance,
each set of bus lines will remain at its last state.
The IN74AC651 has inverted outputs.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0
μA,
0.1
μA
@ 25°C
•
High Noise Immunity Characteristic of CMOS Devices
•
Outputs Source/Sink 24 mA
ORDERING INFORMATION
IN74AC651N Plastic
IN74AC651DW SOIC
T
A
= -40° to 85° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 24=V
CC
PIN 12 = GND
Rev. 00
IN74AC651
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
I
CC
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Sink/Source Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +7.0
-0.5 to V
CC
+0.5
-0.5 to V
CC
+0.5
±20
±50
±50
750
500
-65 to +150
260
Unit
V
V
V
mA
mA
mA
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
J
T
A
I
OH
I
OL
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Junction Temperature (PDIP)
Operating Temperature, All Package Types
Output Current - High
Output Current - Low
Input Rise and Fall Time
*
(except Schmitt Inputs)
V
CC
=3.0 V
V
CC
=4.5 V
V
CC
=5.5 V
0
0
0
-40
Min
2.0
0
Max
6.0
V
CC
140
+85
-24
24
150
40
25
Unit
V
V
°C
°C
mA
mA
ns/V
*
V
IN
from 30% to 70% V
CC
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range GND≤(V
IN
or
V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
Rev. 00
IN74AC651
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Symbol
V
IH
Parameter
Minimum High-
Level Input Voltage
Maximum Low -
Level Input Voltage
Minimum High-
Level Output Voltage
Test Conditions
V
OUT
=0.1 V or V
CC
-0.1 V
V
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
5.5
5.5
Guaranteed Limits
25
°C
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.56
3.86
4.86
0.1
0.1
0.1
0.36
0.36
0.36
±0.1
±0.6
-40°C to
85°C
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.46
3.76
4.76
0.1
0.1
0.1
0.44
0.44
0.44
±1.0
±6.0
μA
μA
V
Unit
V
V
IL
V
OUT
=0.1 V or V
CC
-0.1 V
V
V
OH
I
OUT
≤
-50
μA
V
V
IN
=V
IH
or V
IL
I
OH
=-12 mA
I
OH
=-24 mA
I
OH
=-24 mA
V
OL
Maximum Low-
Level Output Voltage
I
OUT
≤
50
μA
*
V
IN
=V
IH
or V
IL
I
OL
=12 mA
I
OL
=24 mA
I
OL
=24 mA
I
IN
I
OZ
Maximum Input
Leakage Current
Maximum Three-
State Leakage
Current
+Minimum Dynamic
Output Current
+Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
(per Package)
V
IN
=V
CC
or GND
V
IN
(OE)=V
IH
or V
IL
V
IN
=V
CC
or GND
V
OUT
=V
CC
or GND
V
OLD
=1.65 V Max
V
OHD
=3.85 V Min
V
IN
=V
CC
or GND
*
I
OLD
I
OHD
I
CC
5.5
5.5
5.5
8.0
75
-75
80
mA
mA
μA
*
All outputs loaded; thresholds on input associated with output under test.
+Maximum test duration 2.0 ms, one output loaded at a time.
Note: I
IN
and I
CC
@ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V V
CC
Rev. 00
IN74AC651
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=3.0 ns)
V
CC*
Symbol
Parameter
V
Guaranteed Limits
25
°C
Min
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
PLZ
C
IN
C
OUT
Propagation Delay, A-to-B Clock or
B-to-A Clock to A or B Data Port (Figure 1)
Propagation Delay, A-to-B Clock or
B-to-A Clock to A or B Data Port (Figure 1)
Propagation Delay, Input A to Output B or
Input B to Output A (Figures 2,3)
Propagation Delay, Input A to Output B or
Input B to Output A (Figures 2,3)
Propagation Delay, A-to-B Source or
B-to-A Source to A or B Data Port (Figure 4)
Propagation Delay, A-to-B Source or
B-to-A Source to A or B Data Port (Figure 4)
Propagation Delay, Output Enable to A Data
Port (Figure 5)
Propagation Delay, Output Enable to A Data
Port (Figure 5)
Propagation Delay, Output Enable to A Data
Port (Figure 5)
Propagation Delay, Output Enable to A Data
Port (Figure 5)
Propagation Delay, Direction to B Data Port
(Figure 6)
Propagation Delay, Direction to B Data Port
(Figure 6)
Propagation Delay, Direction to B Data Port
(Figure 6)
Propagation Delay, Direction to B Data Port
(Figure 6)
Maximum Input Capacitance
Input/Output Capacitance
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
5.0
5.0
4.0
2.5
3.0
2.0
3.0
2.0
2.5
1.5
3.0
2.5
2.5
2.0
2.5
1.5
2.5
1.5
3.0
2.0
2.5
2.0
3.0
2.0
2.5
1.5
3.5
2.5
3.0
2.5
4.5
15
Max
17.0
12.0
14.5
10.5
14.0
9.5
13.0
9.0
14.0
10.0
13.5
10.0
12.0
9.0
12.0
9.0
13.0
11.0
12.5
10.5
12.5
9.5
12.5
9.5
13.5
11.5
13.5
11.5
-40°C to
85°C
Min
3.0
2.0
2.5
1.5
2.5
1.5
2.0
1.0
2.5
2.0
2.0
1.5
2.0
1.0
2.0
1.0
2.5
1.5
2.0
1.5
2.5
1.5
2.0
1.0
3.0
2.0
2.5
2.0
4.5
15
Max
19.0
14.0
16.5
12.0
16.0
11.0
15.0
10.5
16.0
11.5
15.5
11.5
13.5
10.0
14.0
10.5
14.0
12.0
14.0
12.0
14.0
10.5
14.5
11.0
14.5
12.5
15.0
13.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
Unit
Typical @25°C,V
CC
=5.0 V
C
PD
*
Power Dissipation Capacitance
60
pF
Voltage Range 3.3 V is 3.3 V
±0.3
V
Voltage Range 5.0 V is 5.0 V
±0.5
V
Rev. 00
IN74AC651
TIMING REQUIREMENTS
(C
L
=50pF,Input t
r
=t
f
=3.0 ns)
V
CC*
Symbol
t
su
t
h
t
w
Parameter
Minimum Setup Time, A or B Data Port to A-
to-B Clock or B-to-A Clock (Figure 7)
Minimum Hold Time, A-to-B Clock or
B-to-A Clock to A or B Data Port (Figure 7)
Minimum Pulse Width, A-to-B Clock or
B-to-A Clock (Figure 7)
V
5.0
5.0
5.0
Guaranteed Limits
25
°C
7.0
2.5
6.0
-40°C to
85°C
8.0
2.5
7.0
Unit
ns
ns
ns
TIMING DIAGRAM
Rev. 00
分立器件
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