TECHNICAL DATA
IN74HCT574A
Octal 3-State
Noninverting D Flip-Flop
High-Performance Silicon-Gate CMOS
The IN74HCT574A is identical in pinout to the LS/ALS574. This
device may be used as a level converter for interfacing TTL or NMOS
outputs to High-Speed CMOS inputs.
Data meeting the setup time is clocked to the outputs with the rising
edge of the Clock. The Output Enable input does not affect the states of
the flip-flops, but when Output Enable is high, all device outputs are
forced to the high-impedance state; thus, data may be stored even when
the outputs are not enabled.
•
•
•
•
TTL/NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0
µA
ORDERING INFORMATION
IN74HCT574AN Plastic
IN74HCT574ADW SOIC
T
A
= -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
PIN 20=V
CC
PIN 10 = GND
Output
Enable
L
L
L
H
L,H,
X
Inputs
Clock
D
H
L
X
X
Output
Q
H
L
no
change
Z
X = don’t care
Z = high impedance
Rev. 00
IN74HCT574A
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
I
CC
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +7.0
-1.5 to V
CC
+1.5
-0.5 to V
CC
+0.5
±20
±35
±75
750
500
-65 to +150
260
Unit
V
V
V
mA
mA
mA
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
Min
4.5
0
-55
0
Max
5.5
V
CC
+125
500
Unit
V
V
°C
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range GND≤(V
IN
or
V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
Rev. 00
IN74HCT574A
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Symbol
Parameter
Test Conditions
V
Guaranteed Limit
25
°C
to
-55°C
2.0
2.0
0.8
0.8
4.4
5.4
3.98
0.1
0.1
0.26
±0.1
±0.5
≤85
°C
2.0
2.0
0.8
0.8
4.4
5.4
3.84
0.1
0.1
0.33
±1.0
±5.0
≤125
°C
2.0
2.0
0.8
0.8
4.4
5.4
3.7
0.1
0.1
0.4
±1.0
±10
µA
µA
V
Unit
V
IH
V
IL
V
OH
Minimum High-
Level Input Voltage
Maximum Low -
Level Input Voltage
Minimum High-
Level Output Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
⎢I
OUT
⎢≤
20
µA
V
OUT
=0.1 V or V
CC
-0.1 V
⎢I
OUT
⎢ ≤
20
µA
V
IN
=V
IH
or V
IL
⎢I
OUT
⎢ ≤
20
µA
V
IN
=V
IH
or V
IL
⎢I
OUT
⎢ ≤
6.0 mA
4.5
5.5
4.5
5.5
4.5
5.5
4.5
4.5
5.5
4.5
5.5
5.5
V
V
V
V
OL
Maximum Low-
Level Output Voltage
V
IN
= V
IL
or V
IH
⎢I
OUT
⎢ ≤
20
µA
V
IN
= V
IL
or V
IH
⎢I
OUT
⎢ ≤
6.0 mA
I
IN
I
OZ
Maximum Input
Leakage Current
Maximum Three
State Leakage
Current
Maximum Quiescent
Supply Current
(per Package)
Additional Quiescent
Supply Current
V
IN
=V
CC
or GND
Output in High-Impedance
State
V
IN
=V
IH
or V
IL
V
OUT
= V
CC
or GND
V
IN
=V
CC
or GND
I
OUT
=0µA
V
IN
=2.4 V, Any One Input
V
IN
=V
CC
or GND,
Other Inputs
I
OUT
=0µA
I
CC
5.5
4.0
40
160
µA
∆I
CC
≥-55°C
25°C to
125°C
2.4
mA
5.5
2.9
Rev. 00
IN74HCT574A
AC ELECTRICAL CHARACTERISTICS
(V
CC
=5.0 V
±
10%, C
L
=50pF,Input t
r
=t
f
=6.0 ns)
Guaranteed Limit
Symbol
Parameter
25
°C
to
-55°C
30
30
28
28
12
10
15
≤85°C
≤125°C
Unit
f
max
t
PLH
, t
PHL
t
PLZ
, t
PHZ
t
PZH
, t
PZL
t
TLH
, t
THL
C
IN
C
OUT
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
Maximum Propagation Delay, Clock to Q
(Figures 1 and 4)
Maximum Propagation Delay, Output Enable to
Q (Figures 2 and 5)
Maximum Propagation Delay, Output Enable to
Q (Figures 2 and 5)
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
Maximum Input Capacitance
Maximum Three-State Output Capacitance
(Output in High-Impedance State)
Power Dissipation Capacitance (Per Flip-Flop)
24
38
35
35
15
10
15
20
45
42
42
18
10
15
MHz
ns
ns
ns
ns
pF
pF
Typical @25°C,V
CC
=5.0 V
58
pF
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC2
f+I
CC
V
CC
TIMING REQUIREMENTS
(V
CC
=5.0 V
±
10%, C
L
=50pF,Input t
r
=t
f
=6.0 ns)
Guaranteed Limit
Symbol
t
SU
t
h
t
w
t
r,
t
f
Parameter
Minimum Setup Time, Data to
Clock (Figure 3)
Minimum Hold Time, Clock
to Data (Figure 3)
Minimum Pulse Width, Clock
(Figure 1)
Maximum Input Rise and Fall
Times (Figure 1)
25
°C
to
-55°C
10
5
15
500
≤85°C
13
5
19
500
≤125°C
15
5
22
500
Unit
ns
ns
ns
ns
Rev. 00
IN74HCT574A
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Test Circuit
Figure 5. Test Circuit
EXPANDED LOGIC DIAGRAM
Rev. 00
嵌入式系统
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