TECHNICAL DATA
IN74HCT373A
Octal 3-State Noninverting
Transparent Latch
The IN74HCT373A may be used as a level converter for interfacing
TTL or NMOS outputs to High-Speed CMOS inputs.
The IN74HCT373A is identical in pinout to the LS/ALS373.
The eight latches of the IN74HCT373A are transparent D-type latches.
While the Latch Enable is high the Q outputs follow the Data Inputs.
When Latch Enable is taken low, data meeting the setup and hold times
becomes latched.
The Output Enable does not affect the state of the latch, but when
Output Enable is high, all outputs are forced to the high-impedance state.
Thus, data may be latched even when the outputs are not enabled.
•
TTL/NMOS-Compatible Input Levels
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 4.5 to 5.5 V
•
Low Input Current: 1.0
µA
ORDERING INFORMATION
IN74HCT373AN Plastic
IN74HCT373ADW SOIC
T
A
= -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Output
Enable
PIN 20=V
CC
PIN 10 = GND
L
L
L
H
Latch
Enable
H
H
L
X
D
H
L
X
X
Output
Q
H
L
No Change
Z
X = Don’t Care
Z = High Impedance
Rev. 00
IN74HCT373A
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
I
CC
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air, Plastic DIP**
SOIC Package**
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +7.0
-1.5 to V
CC
+1.5
-0.5 to V
CC
+0.5
±20
±35
±75
750
500
-65 to +150
260
Unit
V
V
V
mA
mA
mA
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
**Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
Min
4.5
0
-55
0
Max
5.5
V
CC
+125
500
Unit
V
V
°C
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range GND≤(V
IN
or
V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
Rev. 00
IN74HCT373A
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Symbol
Parameter
Test Conditions
V
Guaranteed Limit
25
°C
to
-55°C
2.0
2.0
0.8
0.8
4.4
5.4
3.98
0.1
0.1
0.26
±0.1
±0.5
≤85
°C
2.0
2.0
0.8
0.8
4.4
5.4
3.84
0.1
0.1
0.33
±1.0
±5.0
≤125
°C
2.0
2.0
0.8
0.8
4.4
5.4
3.7
0.1
0.1
0.4
±1.0
±10
µA
µA
V
Unit
V
IH
V
IL
V
OH
Minimum High-
Level Input Voltage
Maximum Low -
Level Input Voltage
Minimum High-
Level Output Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
⎢I
OUT
⎢≤
20
µA
V
OUT
=0.1 V or V
CC
-0.1 V
⎢I
OUT
⎢ ≤
20
µA
V
IN
=V
IH
or V
IL
⎢I
OUT
⎢ ≤
20
µA
V
IN
=V
IH
or V
IL
⎢I
OUT
⎢ ≤
6.0 mA
4.5
5.5
4.5
5.5
4.5
5.5
4.5
4.5
5.5
4.5
5.5
5.5
V
V
V
V
OL
Maximum Low-
Level Output Voltage
V
IN
= V
IL
or V
IH
⎢I
OUT
⎢ ≤
20
µA
V
IN
= V
IL
or V
IH
⎢I
OUT
⎢ ≤
6.0 mA
I
IN
I
OZ
Maximum Input
Leakage Current
Maximum Three-
State Leakage
Current
Maximum Quiescent
Supply Current
(per Package)
Additional Quiescent
Supply Current
V
IN
=V
CC
or GND
Output in High-Impedance
State
V
IN
= V
IL
or V
IH
V
OUT
=V
CC
or GND
V
IN
=V
CC
or GND
I
OUT
=0µA
V
IN
=2.4 V, Any One Input
V
IN
=V
CC
or GND,
Other Inputs
I
OUT
=0µA
I
CC
5.5
4.0
40
160
µA
∆I
CC
≥-55°C
25°C to
125°C
2.4
mA
5.5
2.9
Rev. 00
IN74HCT373A
AC ELECTRICAL CHARACTERISTICS
(V
CC
=5.0 V
±
10%, C
L
=50pF, t
r
=t
f
=6.0 ns)
Guaranteed Limit
Symbol
Parameter
25
°C
to
-55°C
28
32
30
35
12
10
15
≤85°C
≤125°C
Unit
t
PLH
, t
PHL
t
PLH
, t
PHL
t
PLZ
, t
PHZ
t
PZL
, t
PZH
t
TLH
, t
THL
C
IN
C
OUT
Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
Maximum Propagation Delay , Latch Enable to Q
(Figures 2 and 5)
Maximum Propagation Delay ,Output Enable to
Q (Figures 3 and 6)
Maximum Propagation Delay , Output Enable to
Q (Figures 3 and 6)
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
Maximum Input Capacitance
Maximum Three-State Output Capacitance
(Output in High-Impedance State)
Power Dissipation Capacitance (Per Latch)
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC2
f+I
CC
V
CC
Minimum Setup Time, Input D to Latch Enable
(Figure 4)
Minimum Hold Time,Latch Enable to Input D
(Figure 4)
Minimum Pulse Width, Latch Enable (Figure 2)
Maximum Input Rise and Fall Times (Figure 1)
35
40
38
44
15
10
15
42
48
45
53
18
10
15
ns
ns
ns
ns
ns
pF
pF
T
A
=25°C,V
CC
=5.0 V
65
pF
C
PD
t
SU
t
h
t
w
t
r,
t
f
10
10
12
500
13
13
15
500
15
15
18
500
ns
ns
ns
ns
Rev. 00
IN74HCT373A
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Switching Waveforms
Figure 5. Test Circuit
Figure 6. Test Circuit
EXPANDED LOGIC DIAGRAM
Rev. 00
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