TECHNICAL DATA
IN74HCT273A
Octal D Flip-Flop with
Common Clock and Reset
High-Performance Silicon-Gate CMOS
The IN74HCT273A is identical in pinout to the LS/ALS273.
The IN74HCT273A may be used as a level converter for interfacing
TTL or NMOS outputs to High-Speed CMOS inputs.
This device consists of eight D flip-flops with common Clock and
Reset inputs. Each flip-flop is loaded with a low-to-high transition of the
Clock input. Reset is asynchronous and active low.
•
TTL/NMOS Compatible Input Levels
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 4.5 to 5.5 V
•
Low Input Current: 1.0
µA
ORDERING INFORMATION
IN74HCT273AN Plastic
IN74HCT273ADW SOIC
T
A
= -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
PIN 20=V
CC
PIN 10 = GND
Reset
L
H
H
H
H
X = don’t care
L
Inputs
Clock
X
D
X
H
L
X
X
Output
Q
L
H
L
no change
no change
Rev. 00
IN74HCT273A
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
I
CC
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +7.0
-1.5 to V
CC
+1.5
-0.5 to V
CC
+0.5
±20
±35
±75
750
500
-65 to +150
260
Unit
V
V
V
mA
mA
mA
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
Min
4.5
0
-55
0
Max
5.5
V
CC
+125
500
Unit
V
V
°C
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range GND≤(V
IN
or
V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
Rev. 00
IN74HCT273A
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Symbol
Parameter
Test Conditions
V
Guaranteed Limit
25
°C
to
-55°C
2.0
2.0
0.8
0.8
4.4
5.4
3.98
0.1
0.1
0.26
±0.1
4.0
≤85
°C
2.0
2.0
0.8
0.8
4.4
5.4
3.84
0.1
0.1
0.33
±1.0
40
≤125
°C
2.0
2.0
0.8
0.8
4.4
5.4
3.7
0.1
0.1
0.4
±1.0
160
µA
µA
V
Unit
V
IH
V
IL
V
OH
Minimum High-
Level Input Voltage
Maximum Low -
Level Input Voltage
Minimum High-
Level Output Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
⎢I
OUT
⎢≤
20
µA
V
OUT
=0.1 V or V
CC
-0.1 V
⎢I
OUT
⎢ ≤
20
µA
V
IN
=V
IH
or V
IL
⎢I
OUT
⎢ ≤
20
µA
V
IN
=V
IH
or V
IL
⎢I
OUT
⎢ ≤
4.0 mA
4.5
5.5
4.5
5.5
4.5
5.5
4.5
4.5
5.5
4.5
5.5
5.5
V
V
V
V
OL
Maximum Low-
Level Output Voltage
V
IN
= V
IL
or V
IH
⎢I
OUT
⎢ ≤
20
µA
V
IN
= V
IL
or V
IH
⎢I
OUT
⎢ ≤
4.0 mA
I
IN
I
CC
Maximum Input
Leakage Current
Maximum Quiescent
Supply Current
(per Package)
Additional Quiescent
Supply Current
V
IN
=V
CC
or GND
V
IN
=V
CC
or GND
I
OUT
=0µA
V
IN
=2.4 V, Any One Input
V
IN
=V
CC
or GND,
Other Inputs
I
OUT
=0µA
∆I
CC
≥-55°C
25°C to
125°C
2.4
mA
5.5
2.9
Rev. 00
IN74HCT273A
AC ELECTRICAL CHARACTERISTICS
(V
CC
=5.0 V
±
10%, C
L
=50pF,Input t
r
=t
f
=6.0 ns)
Guaranteed Limit
Symbol
Parameter
25
°C
to
-55°C
30
25
25
18
10
≤85°C
≤125°C
Unit
f
max
t
PLH
, t
PHL
t
PHL
t
TLH
, t
THL
C
IN
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
Maximum Propagation Delay, Clock to Q
(Figures 1 and 4)
Maximum Propagation Delay , Reset to Q
(Figures 2 and 4)
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
Maximum Input Capacitance
Power Dissipation Capacitance (Per Gate)
24
28
28
20
10
20
35
35
22
10
MHz
ns
ns
ns
pF
Typical @25°C,V
CC
=5.0 V
30
pF
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC2
f+I
CC
V
CC
TIMING REQUIREMENTS
(V
CC
=5.0 V
±
10%, C
L
=50pF,Input t
r
=t
f
=6.0 ns)
Guaranteed Limit
Symbol
t
SU
t
h
t
rec
Parameter
Minimum Setup Time, Data to
Clock (Figure 3)
Minimum Hold Time, Clock
to Data (Figure 3)
Minimum Recovery Time,
Reset Inactive to Clock
(Figure 2)
Minimum Pulse Width, Clock
(Figure 1)
Minimum Pulse Width, Reset
(Figure 2)
Maximum Input Rise and Fall
Times (Figure 1)
25
°C
to
-55°C
10
3.0
5.0
≤85°C
12
3.0
5.0
≤125°C
15
3.0
5.0
Unit
ns
ns
ns
t
w
t
w
t
r,
t
f
12
12
500
15
15
500
18
18
500
ns
ns
ns
Rev. 00
IN74HCT273A
Figure 1. Switching waveforms
Figure 2. Switching waveforms
Figure 3. Switching waveforms
Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
Rev. 00
聊聊、笑笑、闹闹
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
