TECHNICAL DATA
IN74HCT109A
Dual J-K Flip-Flop
with set and Reset
High-Performance Silicon-Gate CMOS
The IN74HCT109A is identical in pinout to the LS/ALS109. The
IN74HCT109A may be used as a level converter for interfacing TTL or
NMOS outputs to High Speed CMOS inputs.
This device consists of two J-K flip-flops with individual set, reset, and
clock inputs. Changes at the inputs are reflected at the outputs with the next
low-to-high transition of the clock. Both Q to Q outputs are available from
each flip-flop.
•
TTL/NMOS Compatible Input Levels
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 4.5 to 5.5 V
•
Low Input Current: 1.0
µA
ORDERING INFORMATION
IN74HCT109AN Plastic
IN74HCT109AD SOIC
T
A
= -55° to 125° C for all packages.
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Set
L
H
L
H
H
H
H
PIN 16=V
CC
PIN 8 = GND
Reset
H
L
L
H
H
H
H
Clock
X
X
X
J
X
X
X
L
H
L
H
K
X
X
X
L
L
H
H
Output
Q
H
L
H
*
L
Q
L
H
H
*
H
Toggle
No Change
H
L
H
H
L
X X No Change
X = Don’t care
*
Both outputs will remain high as long as Set and
Reset are low., but the output states are
unpredictable if Set and Reset go high
simultaneously.
Rev. 00
IN74HCT109A
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
I
CC
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +7.0
-1.5 to V
CC
+1.5
-0.5 to V
CC
+0.5
±20
±25
±50
750
500
-65 to +150
260
Unit
V
V
V
mA
mA
mA
mW
°C
°C
Maximum Ratings are those values beyond witch damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
Min
4.5
0
-55
0
Max
5.5
V
CC
+125
500
Unit
V
V
°C
ns
Rev. 00
IN74HCT109A
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Symbol
Parameter
Test Conditions
V
Guaranteed Limit
25
°C
to
-55°C
2.0
2.0
0.8
0.8
4.4
5.4
≤85
°C
2.0
2.0
0.8
0.8
4.4
5.4
≤125
°C
2.0
2.0
0.8
0.8
4.4
5.4
Unit
V
IH
Minimum High-
Level Input
Voltage
Maximum Low
-Level Input
Voltage
Minimum High-
Level Output
Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
⎢I
OUT
⎢≤
20
µA
V
OUT
=0.1 V or V
CC
-0.1 V
⎢I
OUT
⎢ ≤
20
µA
V
IN
=V
IH
or V
IL
⎢I
OUT
⎢ ≤
20
µA
V
IN
=V
IH
or V
IL
⎢I
OUT
⎢ ≤
4.0 mA
4.5
5.5
4.5
5.5
4.5
5.5
V
V
IL
V
V
OH
V
4.5
4.5
5.5
3.98
0.1
0.1
3.84
0.1
0.1
3.7
0.1
0.1
V
V
OL
Maximum Low-
Level Output
Voltage
V
IN
= V
IL
or V
IH
⎢I
OUT
⎢ ≤
20
µA
V
IN
= V
IL
or V
IH
⎢I
OUT
⎢ ≤4.0
mA
4.5
5.5
0.26
±0.1
0.33
±1.0
0.4
±1.0
µA
I
IN
Maximum Input
Leakage
Current
Maximum
Quiescent
Supply Current
(per Package)
Additional
Quiescent
Supply Current
V
IN
=V
CC
or GND
I
CC
V
IN
=V
CC
or GND
I
OUT
=0µA
5.5
4.0
40
80
µA
∆I
CC
V
IN
= 2.4 V, Any One Input
V
IN
=V
CC
or GND, Other Inputs
I
OUT
=0µA
5.5
≥-55°C
2.9
25°C to
125°C
2.4
µA
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range GND≤(V
IN
or
V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
Rev. 00
IN74HCT109A
AC ELECTRICAL CHARACTERISTICS
(V
CC
=5.5 V
±
10%, C
L
=50pF,Input t
r
=t
f
=6.0 ns)
Guaranteed Limit
Symbol
Parameter
25
°C
to
-55°C
30
35
46
15
10
≤85
°C
24
44
58
19
10
≤125
°C
20
53
69
22
10
Unit
f
max
t
PLH
, t
PHL
t
PHL
t
TLH
, t
THL
C
IN
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
Maximum Propagation Delay , Set or Reset to Q
or Q (Figures 2 and 4)
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
Maximum Input Capacitance
Power Dissipation Capacitance (Per Flip-Flop)
MHz
ns
ns
ns
pF
Typical @25°C,V
CC
=5.0 V
60
pF
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC2
f+I
CC
V
CC
+∆I
CC
V
CC
TIMING REQUIREMENTS
(V
CC
=5.5 V
±
10%, C
L
=50pF,Input t
r
=t
f
=6.0 ns)
Guaranteed Limit
Symbol
t
SU
t
h
t
rec
Parameter
Minimum Setup Time, J or K
to Clock (Figure 3)
Minimum Hold Time, Clock
to J or K (Figure 3)
Minimum Recovery Time, Set
or Reset Inactive to Clock
(Figure 2)
Minimum Pulse Width, Set or
Reset (Figure 2)
Minimum Pulse Width,Clock
(Figure 1)
Maximum Input Rise and Fall
Times (Figure 1)
25
°C
to
-55°C
20
5
5
≤85°C
25
5
5
≤125°C
30
5
5
Unit
ns
ns
ns
t
w
t
w
t
r,
t
f
16
16
500
20
20
500
24
24
500
ns
ns
ns
Rev. 00
IN74HCT109A
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Switching Waveforms
EXPANDED LOGIC DIAGRAM
Rev. 00
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