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IRFC11N50AB

产品描述Power Field-Effect Transistor, 500V, 0.52ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, 0.165 X 0.248 INCH, DIE-3
产品类别分立半导体    晶体管   
文件大小69KB,共3页
制造商Vishay(威世)
官网地址http://www.vishay.com
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IRFC11N50AB概述

Power Field-Effect Transistor, 500V, 0.52ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, 0.165 X 0.248 INCH, DIE-3

IRFC11N50AB规格参数

参数名称属性值
零件包装代码DIE
包装说明UNCASED CHIP, R-XUUC-N2
针数3
Reach Compliance Codeunknown
配置SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压500 V
最大漏源导通电阻0.52 Ω
FET 技术METAL-OXIDE SEMICONDUCTOR
JESD-30 代码R-XUUC-N2
元件数量1
端子数量2
工作模式ENHANCEMENT MODE
最高工作温度150 °C
封装主体材料UNSPECIFIED
封装形状RECTANGULAR
封装形式UNCASED CHIP
极性/信道类型N-CHANNEL
认证状态Not Qualified
表面贴装YES
端子形式NO LEAD
端子位置UPPER
晶体管元件材料SILICON
Base Number Matches1

文档预览

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PD - 94737
IRFC11N50AB
HEXFET
®
Power MOSFET Die in Wafer Form
l
l
l
D
Key Electrical Characteristics (Packaged Part)
c
Parameter
Description
Drain-to-Source Breakdown Voltage
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current
Gate-to-Source Leakage Current
Operating Junction and
Storage Temperature Range
100% Tested at Probe

Available in Chip Pack, Unsawn Wafer
Sawn on Film
‚
Ultra Low On-Resistance
G
S
500V
R
DS(on)
= 0.52Ω
(max.)
5" Wafer
Min.
500V
Typ.
Max.
Test Conditions
V
GS
= 0V, I
D
= 250µA
V
GS
= 10V, I
D
= 6.6A
V
DS
= V
GS
, I
D
= 250µA
V
DS
= 500V, V
GS
=0V, T
J
=25°C
V
(BR)DSS
R
DS(on)
V
GS(th)
I
DSS
I
GSS
T
J
T
STG
–––
2.0V
–––
–––
–––
–––
–––
–––
0.52Ω
4.0V
25µA
±100nA V
GS
= ±30V
-55°C to 150°C Max.
Mechanical Data
Nominal Backmetal Composition, (Thickness)
Nominal Front Metal Composition, (Thickness)
Dimensions
Wafer Diameter
Wafer Thickness, Tolerance
Relevant Die Mechanical Dwg. Number
Minimum Street Width
Reject Ink Dot Size
Recommended Storage Environment
Recommended Die Attach Conditions
Referenced Package Part:
Cr- Ni - Ag, (1kA°-2kA°-2.5kA°)
Al with 1% Si (3.0µm)
0.165" x 0.248"
125 mm, with 100 flat
425 µm
01-5342
0.084 mm
0.51 mm diameter minimum
Store in original container, in dessicated
nitrogen, with no contamination
For optimum electrical results, die attach
temperature should not exceed 300°C
IRFB11N50A
Die Outline
Note:

The above data sheet is based on IR sample testing under certain predetermined and assumed conditions, and is
provided for illustration purposes only. Customers are encouraged to perform testing in actual proposed packaged
and use conditions. IR die products are tested using IR-based quality assurance procedures and are manufac-
tured using IR’s established processes. Programs for customer-specified testing are available upon request. IR
has experienced assembly yields of generally 95% or greater for individual die; however, customer’s results may
vary. Estimates such as those described and set forth in this data sheet for semiconductor die will vary depending
on a number of packaging, handling, use and other factors. Sold die may not perform on an equivalent basis to
standard package products and are therefore offered with a limited warranty as described in IR’s applicable
standard terms and conditions of sale. All IR die sales are subject to IR’s applicable standard terms and conditions
of sale, which are available upon request.
‚
Part number shown is for die in waferform. Contact factory for these other options.
07/18/03
Document Number: 90422
www.vishay.com
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