HY51V65173HGJ-45/5/6I
HY51V65173HGT-45/5/6I
4M x 16Bit EDO DRAM ET Part
PRELIMINARY
DESCRIPTION
This familiy is a 64Mbit dynamic RAM organized 4,194,304 x 16bit configuration with Extented Data Out
mode CMOS DRAMs. Extended data out mode is a kind of page mode which is useful for the read opera-
tion. The advanced circuit and process allow this device to achieve high performance and low power dissi-
pation. Features are access time(45ns or 50ns) and refresh cycle(4K ref) and power consumption(Normal
or low power with self refresh).
Advanced CMOS process as well as circuit techniques for wide operating margins allow this device to
achieve high speed access and high reliability
FEATURES
•
•
•
•
•
Extended data out operation
Read-modify-write capability
Multi-bit parallel test capability
LVTTL(3.3V) compatible inputs and outputs
/RAS only, CAS-before-/RAS, Hidden and self
refresh(L-version) capability
•
•
•
JEDEC standard pinout
50pin plastic SOJ/TSOP-II(400mil)
Single power supply of 3.3V +/- 10%
Battery back up operation(L-version)
•
Fast access time and cycle time
Part No
HY51V65173HG-45I
HY51V65173HG-5I
HY51V65173HG-6I
tRAC
45ns
50ns
60ns
tAA
23ns
25ns
30ns
tCAC
12ns
13ns
15ns
tRC
74ns
84ns
104ns
tHPC
17ns
20ns
25ns
•
Power dissipation
45ns
Active
Standby
468mW
50ns
432mW
60ns
396mW
•
Refresh cycle
Part No
HY51V65173HG*
HY51V65173HGL*
Ref
4K Ref
4K Ref
Normal
64ms
128ms
L-part
1.8mW(CMOS level Max)
0.72mW (L-version : Max)
* : /RAS only, CBR and hidden refresh
ODERING INFORMATION
Part Number
HY51V65173HGJ-45
HY51V65173HGJ-5
HY51V65173HGJ-6
HY51V65173HGT-45I
HY51V65173HGT-5I
HY51V65173HGT-6I
(S) : Self refresh,
(L) : Low power
Access Time
45ns
50ns
60ns
45ns
50ns
60ns
Package
400mil 50pin SOJ
400mil 50pin TSOP-II
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.0.0/Jan.01
HY51V65173HGJ-45/5/6I
HY51V65173HGT-45/5/6I
PIN CONFIGURATION
VCC
IO0
IO1
IO2
IO3
VCC
IO4
IO5
IO6
IO7
NC
VCC
/WE
/RAS
NC
NC
NC
NC
A0
A1
A2
A3
A4
A5
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
VSS
IO15
IO14
IO13
IO12
VSS
IO11
IO10
IO9
IO8
NC
VSS
/LCAS
37 /UCAS
36
35
34
33
32
31
30
29
28
27
26
/OE
NC
NC
NC
A11
A10
A9
A8
A7
A6
VSS
50 Pin Plastic SOJ / TSOP-II
PIN DESCRIPTION
Pin
/RAS
/UCAS, /LCAS
/WE
/OE
A0-A11
A0-A11
I/O 0- I/O 15
Vcc
Vss
NC
Function
Row Address Strobe
Column Address Strobe
Write Enable
Output Enable
Address Inputs
Refresh Address Inputs
Data Input / Output
Power (3.3V)
Ground
No connection
Rev.0.0/Jan.01
2
HY51V65173HGJ-45/5/6I
HY51V65173HGT-45/5/6I
ABSOLUTE MAXIMUM RATINGS
Parameter
Ambient Temperature
Storage Temperature
Voltage on Any Pin relative to V
ss
Voltage on V
cc
relative to V
ss
Short Circuit Output Current
Power Dissipation
Symbol
T
A
T
STG
V
T
V
cc
I
OUT
P
T
Rating
-40 ~ +85
-55 ~ 125
-0.5 ~ Vcc + 0.5
(Max 4.6V)
-0.5 ~ 4.6
50
1
Unit
o
o
C
C
V
V
mA
W
Note :
Operation at above absolute maximum rating can adversely affect device reliability.
Recommended DC OPERATING CONDITIONS
(TA= -40 to 85
o
C)
Parameter
Power Supply Voltage
Power Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
V
cc
V
ss
V
IH
V
IL
Min
3.0
0
2.0
-0.3
Typ.
3.3
0
-
-
Max
3.6
0
V
cc
+ 0.3
0.8
Unit
V
V
V
V
Note
1,2
2
1
1
Note : All voltages are referenced to Vss
1. 6.0V at pulse width 10ns which is measured at Vcc
2. -0.1V at pulse width 10ns which is measured at Vss
Rev.0.0/Jan.01
3
HY51V65173HGJ-45/5/6I
HY51V65173HGT-45/5/6I
DC CHARACTERISTICS
(Vcc = 3.3V +/- 10%, TA= -40 to 85°C)
Symbol
VOH
Output Level
Output Level voltage(Iout= -2mA)
Output Level
Output Level voltage(Iout=2mA)
45ns
ICC1
Parameter
Min
2.4
Max
Vcc
Unit
V
Note
VOL
0
-
-
-
0.4
130
120
110
V
Operating current ( tRC = tRC min)
50ns
60ns
mA
1, 2
I
CC2
Standby current (TTL interface)
Power supply standby current
(/RAS, /UCAS,/LCAS=VIH, Dout = High-Z)
45ns
-
1
mA
-
-
-
-
-
-
-
-
130
120
110
100
90
80
0.5
200
130
120
110
350
uA
4, 5
mA
mA
uA
4
mA
1, 3
mA
2
ICC3
/RAS only refresh current (tRC= tRC min)
50ns
60ns
45ns
ICC4
Extended data out page mode current
(/RAS=VIL, /CAS, Address cycling : tHPC=tHPC min)
50ns
60ns
CMOS interface ( /RAS, /UCAS, /LCAS >= Vcc-0.2V, Dout = High-Z)
ICC5
Standby current ( L-version)
45ns
ICC6
-
-
-
-
/CAS-before-/RAS refresh current (tRC=tRC min)
50ns
60ns
ICC7
Battery back up operating current (standby with CBR)
(tRC=31.25us, tRAS=300ns, Dout=High-Z)
Standby current (CMOS)
Power supply standby current
/RAS=VIH, /UCAS./LCAS=VIL, Dout=Enable)
Self refresh current
(/RAS, /UCAS, /LCAS <=0.2V, Dout=High-Z)
Input leakage current, Any input (0V<= Vin<=Vcc)
Output leakage current, (Dout is disabled, 0V<= Vout<=Vcc)
ICC8
-
5
mA
1
ICC9
II(L)
IO(L)
-
-5
-5
350
5
5
uA
uA
uA
5
Note :
1. Icc depends on output load condition when the device is selected, Icc(max) is specified at the output open condition
2. Address can be changed once or less while RAS=VIL
3. Measured with one sequential address change per EDO cycle, tHPC
4. VIH>=Vcc-0.2V, 0V<=VIL<=0.2V
5. L-Version
Rev.0.0/Jan.01
4
HY51V65173HGJ-45/5/6I
HY51V65173HGT-45/5/6I
CAPACITANCE
(Vcc=3.3V +/-10%, TA=25°C)
Parameter
Input capacitance (Address)
Input capacitance (Clocks)
Output capacitance (Data-in, Data-out)
Symbol
CI1
CI2
CI/O
Min.
-
-
-
Max
5
5
7
Unit
pF
pF
pF
Note
1
1
1, 2
Note : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. /RAS, /UCAS and /LCAS = V
IH
to disable D
out
AC CHARACTERISTICS
Test Condition
•
•
(Vcc=3.3V +/-10%, TA= -40~85C, Note 1, 2, 19,20)
•
Input rise and fall times = 2ns
Input level : V
IL
/V
IH
= 0.0 / 0.3V
Input timing reference level : V
IL
/V
IH
= 0.8/2.0V
•
•
Output timing reference level :
V
OL
/V
OH
=0.8/0.2V
Output load : 1 TTL gate + C
L
(100pF)
including scope and jig
Read, Write, Read-modify-Write and Refresh Cycles
-45I
Parameter
Random read or write cycle time
/RAS precharge time
/CAS precharge time
/RAS pulse width
/CAS pulse width
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
/RAS to /CAS delay time
/RAS to Column address delay time
/RAS hold time
/CAS hold time
/CAS to /RAS precharge time
Symbol
Min
t
RC
t
RP
t
CP
t
RAS
t
CAS
t
ASR
t
RAH
t
ASC
t
CAH
t
RCD
t
RAD
t
RSH
t
CSH
t
CRP
74
25
7
45
7
0
7
0
7
11
9
12
38
5
Max
-
-
-
10,000
10,000
-
-
-
-
33
22
-
-
-
Min
84
30
8
50
8
0
8
0
8
12
10
13
40
5
Max
-
-
-
10,000
10,000
-
-
-
-
37
25
-
-
-
Min
104
40
10
60
10
0
10
0
10
14
12
15
42
5
Max
-
-
-
10,000
10,000
-
-
-
-
45
30
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
22
21
21
3
4
24
-5I
-6I
Unit
Note
Rev.0.0/Jan.01
5
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