TECHNICAL DATA
IN74HC574A
Octal 3-State
Noninverting D Flip-Flop
High-Performance Silicon-Gate CMOS
N SUFFIX
PLASTIC DIP
The IN74HC574A is identical in pinout to the LS/ALS574. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
Data meeting the setup time is clocked to the outputs with the rising
edge of the Clock. The OE input does not affect the states of the flip-
flops, but when OE is high, all device outputs are forced to the high-
impedance state; thus, data may be stored even when the outputs are not
enabled.
•
•
•
•
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
μA
High Noise Immunity Characteristic of CMOS Devices
20
1
20
1
DW SUFFIX
SOIC
ORDERING INFORMATION
IN74HC574AN
IN74HC574ADW
IN74HC574ATDS
Plastic DIP
SOIC
SOIC
T
A
= -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
OE
D0
D1
D0
D1
D2
DATA
INPUTS
D3
D4
D5
D6
D7
CLOCK
2
3
4
5
6
7
8
9
11
19
18
17
16
15
14
13
12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
NONINVERTING
OUTPUTS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V CC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CLOCK
D2
D3
D4
D5
D6
D7
GND
FUNCTION TABLE
Inputs
Output
D
H
L
L,H,
X
X
X
Q
H
L
no
change
Z
OE
PIN 20=V
CC
PIN 10 = GND
L
L
L
H
Clock
1
OE
H= high level
L = low level
X = don’t care
Z = high impedance
Rev. 00
IN74HC574A
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
I
CC
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Storage Temperature
Lead Temperature, 1.5 mm from Case for 4 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +7.0
-1.5 to V
CC
+1.5
-0.5 to V
CC
+0.5
±20
±35
±75
750
500
-65 to +150
260
Unit
V
V
V
mA
mA
mA
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time
(Figure 1)
V
CC
=2.0 V
V
CC
=4.5 V
V
CC
=6.0 V
Min
2.0
0
-55
0
0
0
Max
6.0
V
CC
+125
1000
500
400
Unit
V
V
°C
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range GND≤(V
IN
or
V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
Rev. 00
IN74HC574A
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
C
C
Guaranteed Limit
25
°C
to
-55°C
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±0.1
±0.5
≤85
°C
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1.0
±5.0
≤125
°C
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1.0
±10
μA
μA
V
Unit
V
Symbol
V
IH
Parameter
Minimum High-Level
Input Voltage
Maximum Low -Level
Input Voltage
Minimum High-Level
Output Voltage
Test Conditions
V
OUT
≥
V
CC
-0.1 V
⎢I
OUT
⎢≤
20
μA
V
OUT
⎢ ≤
0.1 V
⎢I
OUT
⎢ ≤
20
μA
V
IN
=V
IH
⎢I
OUT
⎢ ≤
20
μA
V
IN
=V
IH
⎢I
OUT
⎢ ≤
6.0 mA
⎢I
OUT
⎢ ≤
7.8 mA
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
V
IL
V
V
OH
V
V
OL
Maximum Low-Level
Output Voltage
V
IN
= V
IL
⎢I
OUT
⎢ ≤
20
μA
V
IN
= V
IL
⎢I
OUT
⎢ ≤
6.0 mA
⎢I
OUT
⎢ ≤7.8
mA
I
IN
I
OZ
Maximum Input
Leakage Current
Maximum Three State
Leakage Current
V
IN
=V
CC
or GND
Output in High-Impedance
State
V
IN
=V
IH
V
OUT
= V
CC
or GND
V
IN
=V
CC
or GND
I
OUT
=0μA
I
CC
Maximum Quiescent
Supply Current
(per Package)
6.0
4.0
40
160
μA
Rev. 00
IN74HC574A
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
f
max
Parameter
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
Maximum Propagation Delay, Clock to Q
(Figures 1 and 4)
Maximum Propagation Delay, Output Enable to
Q (Figures 2 and 5)
Maximum Propagation Delay, Output Enable to
Q (Figures 2 and 5)
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
Maximum Input Capacitance
Maximum Three-State Output Capacitance
(Output in High-Impedance State)
Power Dissipation Capacitance (Per Enabled
Output)
C
PD
Used to determine the no-load dynamic power
consumption: P
D
=C
PD
V
CC2
f+I
CC
V
CC
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
-
-
Guaranteed Limit
25
°C
to
-55°C
6.0
30
35
160
32
27
150
30
26
140
28
24
60
12
10
10
15
≤85°C
4.8
24
28
200
40
34
190
38
33
175
35
30
75
15
13
10
15
≤125°
C
4.0
20
24
240
48
41
225
45
38
210
42
36
90
18
15
10
15
Unit
MHz
t
PLH
, t
PHL
ns
t
PLZ
, t
PHZ
ns
t
PZH
, t
PZL
ns
t
TLH
, t
THL
ns
C
IN
C
OUT
pF
pF
Typical @25°C,V
CC
=5.0 V
24
pF
TIMING REQUIREMENTS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
t
SU
Parameter
Minimum Setup Time, Data to
Clock (Figure 3)
Minimum Hold Time, Clock to
Data (Figure 3)
Minimum Pulse Width, Clock
(Figure 1)
Maximum Input Rise and Fall
Times (Figure 1)
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
25
°C
to
-55°C
50
10
9
5
5
5
75
15
13
1000
500
400
Guaranteed Limit
≤85°C
65
13
11
5
5
5
95
19
16
1000
500
400
≤125°C
75
15
13
5
5
5
110
22
19
1000
500
400
Unit
ns
t
h
ns
t
w
ns
t
r,
t
f
ns
Rev. 00
IN74HC574A
tr
CLOCK
90%
50%
10%
tf
V
CC
V
CC
GND
OE
t
PZL
Q
t
PHL
Q
t
THL
t
PZH
50%
50%
50%
GND
t
PLZ
10%
t
PHZ
90%
HIGH
IMPEDANCE
V
OL
V
OH
HIGH
IMPEDANCE
t
w
1/fmax
t
PLH
Q
50%
10%
90%
t
TLH
Figure 1. Switching Waveforms
VALID
D
Figure 2. Switching Waveforms
V
CC
50%
GND
t
su
CLOCK
50%
t
h
V
CC
GND
Figure 3. Switching Waveforms
TEST POINT
TEST POINT
1k
C
L
*
DEVICE
UNDER
TEST
OUTPUT
C
L
*
DEVICE
UNDER
TEST
OUTPUT
Connect to V
CC
when
testing t
PLZ
and t
PZL
Connect to GND when
testing t
PHZ
and t
PZH
* Includes all probe and jig capacitance
Figure 4. Test Circuit
* Includes all probe and jig capacitance
Figure 5. Test Circuit
EXPANDED LOGIC DIAGRAM
D0
D1
D2
D3
D4
D5
D6
D7
D
C Q
CLOCK
D
C Q
D
C Q
D
C Q
D
C Q
D
C Q
D
C Q
D
C Q
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Rev. 00
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
