The LCK4993 and LCK4994 low-voltage PLL clock drivers
offer user-selectable control over system clock functions.
The multiple-output clock drivers provide the system
integrator with functions necessary to optimize the timing of
high-performance computer and communication systems.
Each of the eighteen configurable outputs drive terminated
transmission lines with impedances as low as 50
Ω
while
delivering minimal and specified output skews at LVTTL
levels. The outputs are arranged in five banks. Banks 1—4
allow a divide function of 1 to 12, while simultaneously
allowing phase adjustments in 625 ps—1300 ps increments
up to 10.4 ns. One of the output banks also includes an
independent clock invert function. The feedback bank
consists of two outputs that allow divide-by functionality
from 1 to 12 and limited phase adjustments. Any one of
these eighteen outputs can be connected to the feedback
input or drive other inputs.
Selectable reference input is a fault tolerance feature that
allows smooth change over to the secondary clock source
when the primary clock source is not in operation. The
reference inputs and feedback inputs are configurable to
accommodate both LVTTL or differential (LVPECL) inputs.
The completely integrated PLL reduces jitter and simplifies
board layout.
12 MHz—100 MHz (LCK4993), or 24 MHz—200 MHz
(LCK4994) output operation
Matched pair output skew <200 ps
Zero input-to-output delay
18 LVTTL 50% duty-cycle outputs capable of driving
50
Ω
terminated lines
3.3 V/2.5 V LVTTL/LV differential (LVPECL) fault tolerant
and hot insertable reference inputs
Phase adjustments from 625 ps up to 1300 ps steps up
to ±10.4 ns
Output divide ratios of (1—6, 8, 10, 12)
Multiply ratios of (1—6, 8) x input frequency
Individual output bank disable for aggressive power
management and EMI reduction
Output high-impedance (HI-Z) option for testing
purposes
Fully integrated PLL with lock indicator
Single 3.3 V/2.5 V ± 10% supply
100-pin TQFP package
100-ball FSBGA package
Pin-for-pin compatible with
CYPRESS
®
CY7B993V and
CY7B994V
s
s
s
s
s
s
s
s
s
s
s
s
s
s
LCK4993/LCK4994
Low-Voltage PLL Clock Drivers
Data Sheet, Revision 1
May 5, 2004
Table of Contents
Contents
Page
1 Features .............................................................................................................................................................................1
4 Pin Information ...................................................................................................................................................................4
5.1 Phase Frequency Detector and Filter ..........................................................................................................................7
5.2 VCO, Control Logic, Divider, and Phase Generator ....................................................................................................7
5.3 Time Unit Definition .....................................................................................................................................................7
5.4 Divide and Phase Select Matrix ...................................................................................................................................8
5.5 Timing Relationship of Programmable Skew Outputs .................................................................................................9
5.7 INV3 Pin Function ......................................................................................................................................................10
5.9 Factory Test Mode Description ..................................................................................................................................11
5.9.1 Factory Test Reset ...........................................................................................................................................11
5.10 Absolute Maximum Ratings .....................................................................................................................................11
7.2 ac Test Loads and Waveforms ..................................................................................................................................21
7.3 ac Timing Diagrams ...................................................................................................................................................22
9 Ordering Information .........................................................................................................................................................25
Table 5-1. Frequency Range Select .......................................................................................................................................7
Table 5-2. N Factor Determination..........................................................................................................................................7
Table 5-3. Output Skew Select Function ................................................................................................................................8
Table 5-4. Output Divider Function .........................................................................................................................................8
Table 5-6. Factory Test Mode Frequency Divide Select ....................................................................................................... 11
Table 5-7. Absolute Maximum Ratings ................................................................................................................................. 11
Figure 5-1. Typical Outputs with FB Connected to a Zero-Skew Output................................................................................9
Figure 7-1. ac Test Loads and Waveforms ..........................................................................................................................21
Figure 7-2. ac Timing Diagrams ...........................................................................................................................................22
2
Agere Systems Inc.
Data Sheet, Revision 1
May 5, 2004
LCK4993/LCK4994
Low-Voltage PLL Clock Drivers
3 Functional Block Diagram
FBKA+
FBKA–
FBKB+
FBKB–
FBSEL
REFA+
REFA–
REFB+
REFB–
REFSEL
LOCK
PHASE
FREQUENCY
DETECTOR
V
CO
CONTROL LOGIC
DIVIDE AND PHASE
GENERATOR
FILTER
FS
3
3
OUTPUT_MODE
FBF0
FBDS0
FBDS1
FBDIS
4F0
4F1
4DS0
4DS1
DIS4
3F0
BANK 3
3F1
3DS0
3DS1
DIS3
INV3
2F0
2F1
2DS0
2DS1
DIS2
1F0
BANK 1
1F1
1DS0
1DS1
DIS1
3
3
3
FEEDBACK BANK
DIVIDE AND
PHASE SELECT
MATRIX
QFA0
QFA1
3
3
3
3
3
3
3
3
DIVIDE AND
PHASE SELECT
MATRIX
DIVIDE AND
PHASE SELECT
MATRIX
BANK 4
4QA0
4QA1
4QB0
4QB1
3QA0
3QA1
3QB0
3QB1
3
3
3
3
3
3
3
3
DIVIDE AND
PHASE SELECT
MATRIX
DIVIDE AND
PHASE SELECT
MATRIX
BANK 2
2QA0
2QA1
2QB0
2QB1
1QA0
1QA1
1QB0
1QB1
Figure 3-1. LCK4993 and LCK4994 Functional Block Diagram
Agere Systems Inc.
3
LCK4993/LCK4994
Low-Voltage PLL Clock Drivers
Data Sheet, Revision 1
May 5, 2004
4 Pin Information
4.1 100-Pin
TQFP
Diagram
LOCK
FBDS1
FBDS0
GND
1QB1
V
DDN
1QB0
GND
GND
1QA1
V
DDN
1QA0
GND
GND
QFA0
V
DDN
QFA1
GND
GND
FBKB+
FBKB–
FBSEL
FBKA–
FBKA+
V
DDQ
100
99
98
97
96
95
26
27
28
29
30
31
32
33
34
35
36
37
38
GND
GND
GND
V
DDQ
V
DDQ
2F1
1F1
DIS1
DIS2
GND
3QA0
V
DDN
3QA1
GND
GND
3QB0
V
DDN
3QB1
GND
V
DDQ
INV3
GND
OUTPUT_MODE
5-8885 (F) r.1
Figure 4-1. 100-Pin TQFP Package (Top View)
Table 4-1. 100-Pin FSBGA Pin Assignments
1
A
B
C
D
E
F
G
H
J
K
1QB1
V
DDN
GND
LOCK
4QB1
4QB0
4QA1
2
1QB0
V
DDN
GND
4F0
V
DDN
V
DDN
2DS1
3
1QA1
V
DDN
GND
3F1
4DS1
3DS1
V
DDQ
4
1QA0
V
DDN
GND
GND
GND
GND
GND
5
QFA0
V
DDN
GND
FBDS1
3F0
GND
GND
6
QFA1
V
DDN
GND
FBDS0
4F1
GND
GND
7
FBKB+
V
DDQ
V
DD
Q
2F0
GND
GND
GND
V
DDQ
GND
39
40
41
42
43
44
45
46
47
48
49
50
GND
3F1
4F1
3F0
4F0
4DS1
3DS1
GND
4QB1
V
DDN
4QB0
GND
GND
4QA1
V
DDN
4QA0
GND
2DS1
1DS1
V
DDQ
4DS0
3DS0
2DS0
1DS0
GND
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
V
DDQ
REFA+
REFA–
REFSEL
REFB–
REFB+
2F0
FS
GND
2QA0
V
DDN
2QA1
GND
GND
2QB0
V
DDN
2QB1
GND
FBF0
1F0
GND
V
DDQ
FBDIS
DIS4
DIS3
8
V
DD
Q
FBKB–
GND
V
DDQ
FS
FBF0
V
DDQ
9
FBKA–
FBSEL
GND
REFSEL
V
DDN
V
DDN
1F0
10
FBKA+
REFA+
REFA–
REFB–
REFB+
2QA0
2QA1
4QA0
1DS1
1DS0
V
DDQ
GND
GND
V
DDQ
OUTPUT_
MODE
INV3
3QB0
FBDIS
2QB0
4DS0
2F1
3DS0
1F1
2DS0
DIS2
DIS1
V
DDN
V
DDN
3QA0
V
DDN
3QA1
GND
GND
DIS3
3QB1
2QB1
DIS4
4
Agere Systems Inc.
Data Sheet, Revision 1
May 5, 2004
4.2 Pin Descriptions
LCK4993/LCK4994
Low-Voltage PLL Clock Drivers
For all 3-state inputs, low indicates a connection to GND, mid indicates an open connection, and high indicates a
connection to V
DD
. Internal termination circuitry holds an unconnected input to V
DD
/2.
Table 4-2. 100-Pin TQFP Descriptions
Pin
1, 8, 12, 13, 17, 25—28,
35, 39, 40, 44, 47, 50,
55, 58, 62, 63, 67, 82,
83, 87, 88, 92, 93, 97
2—5, 31, 32, 56, 69
6, 7, 18, 19, 21—24
9, 11, 14, 16, 36, 38, 41,
43, 59, 61, 64, 66, 89,
91, 94, 96
10, 15, 37, 42, 60, 65,
85, 90, 95
20, 29, 30, 45, 49, 54,
75, 76
33, 34, 51, 52
Symbol
GND
Type
Power
I/O
—
Ground.
Description
[1:4]F[0:1]
[1:4]DS[0:1]
[1:4]Q[A:B][0:1]
3-Level
Input
3-Level
Input
LVTTL
V
DDN
V
DDQ
DIS[1:4]
Power
Power
LVTTL
Output Phase Function Select.
Each pair controls the phase
function of the respective bank of outputs, see
Table 5-3.
I
Output Divider Function Select.
Each pair controls the divide
function of the respective bank of outputs, see
Table 5-4.
O
Clock Output.
These outputs provide numerous divide and
phase select functions determined by the [1:4]DS[0:1] and
[1:4]F[0:1] inputs.
—
Output Buffer Power.
Power supply for each output pair.
—
Internal Power.
Power supply for the internal circuitry.
I
d
Output Disable.
Each input controls the state of the respective
output bank.
Low = the [1:4]Q[A:B][0:1] is enabled, see
Table 5-5.
High = the output bank is disabled to the hold-off or HI-Z state;
the disable state is determined by OUTPUT_MODE.
Invert Mode.
This input only affects Bank3.
Low = each matched output pair will become complementary
(3QA0+, 3QA1–, 3QB0+, 3QB1–).
Mid = all four outputs will be noninverting.
High = all four outputs in the same bank will be inverted.
Output Mode.
This pin determines the clock outputs’ disable
state.
Low = the clock outputs will disable to hold-off mode.
Mid = the device enters factory test mode.
High = the clock outputs will disable to HI-Z.
Feedback Disable.
This input controls the state of QFA[0:1].
Low = the QFA[0:1] is enabled, see
Table 5-5.
High = the QFA[0:1] is disabled to the hold-off or HI-Z state; the
disable state is determined by OUTPUT_MODE.
Feedback Output Phase Function Select.
This input deter-
mines the phase function of the feedback banks QFA[0:1] out-
puts, see
Table 5-3.
Frequency Select.
This input must be set according to the
nominal frequency (f
NOM
), see
Table 5-1).
Reference Inputs.
These inputs can operate as differential
PECL or single-ended TTL reference inputs to the PLL. When
operating as a single-ended LVTTL input, the complementary
1. 内容简介 在2015年，苹果新一代的MacBook和Apple Watch皆搭载压力触控感应技术，它被Apple称为Force Touch，用户每次按下触控板之后除了可以在萤幕看见视觉回馈，它同时能够分辨出用户点按的力度强弱来做出一系列的相关操控与应用。而本文将介绍以HY16F184内建高精密Sigma-delta 24 Bit ADC搭配Uneo Force Sensor来实现一...[详细]
stm32/stm8
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
