TECHNICAL DATA
IN74HC323A
8-Bit Bidirectional Universal
Shift Register with Parallel I/O
High-Performance Silicon-Gate CMOS
The IN74HC323A is identical in pinout to the LS/ALS323. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
The IN74HC323A features a multiplexed parallel input/output data
port to active full 8-bit handling in a 20 pin package. Due to the large
output drive capability and the 3-state feature, this device is ideally suited
for interface with bus lines in a bus-oriented system.
Two Mode-Select inputs and two Output Enable inputs are used to
choose the mode of operation as listed in the Function Table.
Synchronous parallel loading is accomplished by taking both Mode-
Select lines, S
1
and S
2
, high. This places the outputs in the high-
impedance state, which permits data applied to the data port to be clocked
into the register. Reading out of the register can be accomplished when
the outputs are enabled. The active-low synchronous Reset overrides all
other inputs.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0
µA
•
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
IN74HC323AN Plastic
IN74HC323ADW SOIC
T
A
= -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 20=V
CC
PIN 10 = GND
Rev. 00
IN74HC323A
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
I
CC
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +7.0
-1.5 to V
CC
+1.5
-0.5 to V
CC
+0.5
±20
±35
±75
750
500
-65 to +150
260
Unit
V
V
V
mA
mA
mA
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time
(Figure 1)
V
CC
=2.0 V
V
CC
=4.5 V
V
CC
=6.0 V
Min
2.0
0
-55
0
0
0
Max
6.0
V
CC
+125
1000
500
400
Unit
V
V
°C
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range GND≤(V
IN
or
V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open. I/O pins must be connected to a properly terminated line or bus.
Rev. 00
IN74HC323A
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Symbol
Parameter
Test Conditions
V
Guaranteed Limit
25
°C
to
-55°C
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.98
5.48
3.98
5.48
0.1
0.1
0.1
0.26
0.26
0.26
0.26
±0.1
±0.5
≤85
°C
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.84
5.34
3.84
5.34
0.1
0.1
0.1
0.33
0.33
0.33
0.33
±1.0
±5.0
≤125
°C
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.7
5.2
3.7
5.2
0.1
0.1
0.1
0.4
0.4
0.4
0.4
±1.0
±10
µA
µA
V
Unit
V
IH
Minimum High-
Level Input Voltage
Maximum Low -
Level Input Voltage
Minimum High-
Level Output Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
⎢I
OUT
⎢≤
20
µA
V
OUT
=0.1 V or V
CC
-0.1 V
⎢I
OUT
⎢ ≤
20
µA
V
IN
=V
IH
or V
IL
⎢I
OUT
⎢ ≤
20
µA
V
IN
=V
IH
or V
IL
⎢I
OUT
⎢ ≤
6.0 mA (P/Q)
⎢I
OUT
⎢ ≤
7.8 mA (P/Q)
V
IN
=V
IH
or V
IL
⎢I
OUT
⎢ ≤
4.0 mA (Q’)
⎢I
OUT
⎢ ≤
5.2 mA (Q’)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
4.5
6.0
6.0
6.0
V
V
IL
V
V
OH
V
V
OL
Maximum Low-
Level Output Voltage
V
IN
= V
IL
or V
IH
⎢I
OUT
⎢ ≤
20
µA
V
IN
=V
IH
or V
IL
⎢I
OUT
⎢ ≤
6.0 mA (P/Q)
⎢I
OUT
⎢ ≤
7.8 mA (P/Q)
V
IN
=V
IH
or V
IL
⎢I
OUT
⎢ ≤
4.0 mA (Q’)
⎢I
OUT
⎢ ≤
5.2 mA (Q’)
I
IN
I
OZ
Maximum Input
Leakage Current
Maximum Three-
State Leakage
Current
(Q
A
thru Q
H
)
Maximum Quiescent
Supply Current
(per Package)
V
IN
=V
CC
or GND
Output in High-Impedance
State
V
IN
= V
IL
or V
IH
V
OUT
=V
CC
or GND
V
IN
=V
CC
or GND
I
OUT
=0µA
I
CC
6.0
8.0
80
160
µA
Rev. 00
IN74HC323A
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
Parameter
V
Guaranteed Limit
25
°C
to
-55°C
5.0
25
29
170
34
29
160
32
27
150
30
26
150
30
26
60
12
10
75
15
13
10
15
≤85
°C
4.0
20
24
215
43
37
200
40
34
190
38
33
190
38
33
75
15
13
95
19
16
10
15
≤125
°C
3.4
17
20
255
51
43
240
48
41
225
45
38
225
45
38
90
18
15
110
22
19
10
15
Unit
f
max
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 5)
Maximum Propagation Delay, Clock to Q
A
’ or
Q
H
’ (Figures 1 and 5)
Maximum Propagation Delay, Clock to Q
A
or Q
H
(Figures 1 and 5)
Maximum Propagation Delay , OE1, OE2, S1, or
S2 to Q
A
thru Q
H
(Figures 3 and 6)
Maximum Propagation Delay , OE1, OE2, S1, or
S2 to Q
A
thru Q
H
(Figures 3 and 6)
Maximum Output Transition Time, Q
A
thru Q
H
(Figures 1 and 5)
Maximum Output Transition Time, Q
A
’ or Q
H
’
(Figures 1 and 5)
Maximum Input Capacitance
Maximum Three-State Output Capacitance
(Output in High-Impedance State), Q
A
thru Q
H
Power Dissipation Capacitance (Per Package),
Outputs Enable
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
-
-
MHz
t
PLH
, t
PHL
ns
t
PLH
, t
PHL
ns
t
PLZ
, t
PHZ
ns
t
PZL
, t
PZH
ns
t
TLH
, t
THL
ns
t
TLH
, t
THL
ns
C
IN
C
OUT
pF
pF
Typical @25°C,V
CC
=5.0 V
240
pF
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC2
f+I
CC
V
CC
Rev. 00
IN74HC323A
TIMING REQUIREMENTS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
t
su
Parameter
Minimum Setup Time, Mode Select
S1 or S2 to Clock (Figure 4)
Minimum Setup Time, Data Inputs
S
A
, S
H
, P
A
thru P
H
to Clock
(Figure 4)
Minimum Hold Time, Clock to Mode
Select S1 or S2 (Figure 4)
Minimum Hold Time, Clock to Data
Inputs, S
A
, S
H
, P
A
thru P
H
(Figure 4)
Minimum Pulse Width, Clock
(Figure 1)
Minimum Pulse Width, Reset (Figure
2)
Maximum Input Rise and Fall Times
(Figure 1)
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
100
20
17
100
20
17
120
24
20
5
5
5
80
16
14
80
16
14
1000
500
400
Guaranteed Limit
25
°C
to-55°C
≤85°C
125
25
21
125
25
21
150
30
26
5
5
5
100
20
17
100
20
17
1000
500
400
≤125°C
150
30
26
150
30
26
180
36
31
5
5
5
120
24
20
120
24
20
1000
500
400
Unit
ns
t
su
ns
t
h
ns
t
h
ns
t
w
ns
t
w
ns
t
r
, t
f
ns
Rev. 00
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