CONVERTING DESIGNS USING
THE LXT384 TO THE IDT82V2048
1.0 GENERAL DESCRIPTION
The IDT82V2048 is a full featured octal T1/E1 line interface unit and is
a pin compatible, functional superset of the Intel (previously Level One)
LXT384, octal T1/E1 LIU. Both devices provide the same register map-
ping and functions during normal operation. In addition, the IDT82V2048
offers an expanded register bank to allow increased flexibility and func-
tionality when using a host controller. Converting designs using the
LXT384 to the IDT82V2048 is a straightforward process involving mini-
mal hardware changes. Software adjustments need only be made in
applications where it is intended to access the enhanced register set of
the IDT device. The primary purpose of this application note is to
describe the differences between the LXT384 and the IDT82V2048 and
highlight the design considerations that come into play when converting
an existing LXT384 design.
APPLICATION NOTE
AN-346
2.0 REGISTERS
The register sets of the IDT82V2048 can be divided into Primary Reg-
isters and Expanded Registers. The Primary Registers of the
IDT82V2048 are the same as those of the LXT384, with an added
ADDP (Address Pointer) register. The address of the ADDP register in
the IDT device is 1F (Hex), which is a reserved address in the LXT384.
Writing "AA Hex" to this register will switch to the Expanded Registers of
the IDT82V2048. (Table
1
shows the Registers in the LXT384 and the
Primary Registers in the IDT82V2048).
The functions controlled by the Expanded Registers are available only
with the IDT device as the LXT384 does not offer these registers. Thus,
when using only the Primary Registers, the two devices are completely
software compatible but to take advantage of IDTís additional features
and flexibility some software must be added to source code written for
the LXT384. Table 2 shows the Expanded Registers of the IDT82V2048.
Writing "00 Hex" to the "Address Pointer " register will switch back to Pri-
mary Registers.
Table 1. Primary Register
Address (Hex)
00 - 15
16 - 1E
1F
LXT384
Registers
Reserved
Reserved
IDT82V2048
Primary Registers
Reserved
ADDP (Address Pointer), write "AA Hex" to this register will switch to Expanded Registers.
Table 2. Expanded Register
Address (Hex)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10 - 1E
1F
Register Name
e-SING (Single Rail Mode Setting)
e-CODE (Encoder/Decoder Selection)
e-CRS (Clock Recovery Enable/Disable)
e-RPDN (Receiver Power Down Enable/Disable)
e-TPDN (Transmitter Power Down Enable/Disable)
e-CZER (Consecutive Zero Detect Enable/Disable)
e-CODV (Code Violation Detect Enable/Disable)
e-EQUA (Equalizer Enable/Disable)
e-LBCF (In-band Loop-back Configuration)
e-LBAC (In-band Loop-back Activation Code)
e-LBDC (In-band Loop-back Deactivation Code)
e-LBS (In-band Loop-back Code Receive Status)
e-LBM (In-band Loop-back Interrupt Mask)
e-LBI (In-band Loop-back Activation/Deactivation)
e-LBGS (In-band Loop-back Activation/Deactivation Code Generator Selection)
e-LBGE (In-band Loop-back Activation/Deactivation Code Generator Enable)
Registers for testing. Default is 0, users should not change the default value
ADDP, writing "00 Hex" to this register will switch to Primary Registers
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MAY 2002
1
2002 Integrated Device Technology, Inc.
CONVERTING DESIGNS USING THE LXT384 TO THE IDT82V2048
IDTAPPLICATIONNOTE AN-346
3.0 WORKING WITHOUT MCLK
When MCLK is not available (High/Low), the Receive Path of the
IDT82V2048 is the same as the LXT384, but the Transmit Path is differ-
ent. For the IDT82V2048, if MCLK is not available, TCLK1 will be inter-
nally used as a virtual MCLK for the Transmit Path (The status of the
Receive Path is still determined by the real MCLK pin). As a result, simi-
lar operation can be achieved without an MCLK signal but, in this case,
care must be taken to always supply TCLK1 for normal operation. If nei-
ther MCLK nor TCLK1 is available, the IDT82V2048 will put all the
TTIPn and TRINGn pins into high impedance states. These operation
modes are tabulated below.
4.0 EXTERNAL COMPONENTS
The transmit impedance on the line side between the IDT82V2048 and
the LXT384 is slightly different. When converting an LXT384 design to
the IDT82V2048, the performance will be better if the external transmit
resisters and capacitor are modified. The recommended application cir-
cuit for the IDT82V2048 is shown in
Figure-1.
It is the same as that of
the LXT384, except that the value of RT is 9.5 Ohm +/- 1%. The LXT384
datasheet recommends an RT value of 11 Ohm + 1%. In addition, the
recommended value of CP is 560 pF for the LXT384, whereas IDT rec-
ommends using a CP value that is tuned to the line condition.
Table 3. MCLK and TCLK
MCLK
TCLKn
(n=0-7 for LXT384)
(n=0,2-7 for 2048)
H
Clocked
Operation Mode of the Transmit Path
LXT384
Transmit pulse-shaping is dis-
abled.
Transmit with pulse-shaping
TCLK1 is clocked
TCLK1 is H/L
TCLK1 is clocked
TCLK1 is H/L
IDT82V2048
Transmit all ones
Transmit is high impedance
Transmit with pulse-shaping
Transmit is high impedance
H/L
H/L
2:1
• •
R
X
Line
0.22µF
•
•
1kΩ
R
R
R
R
RTIPn
One of Eight Identical
Channels
•
2:1
• •
T
X
Line
C
T
RRINGn
·
TTIPn
IDT82V2048
1kΩ
VDDT
D4
R
T
D3
VDDT
D2
VDDT
VDDDn
0.1µF
GNDTn
•
•
68µF
R
T
D1
·
TRINGn
Figure 1. Recommended Application Circuit
2
CONVERTING DESIGNS USING THE LXT384 TO THE IDT82V2048
IDTAPPLICATIONNOTE AN-346
5.0 JITTER ATTENUATOR 3DB CORNER FRE-
QUENCY
The selection of the jitter attenuator 3dB corner frequency is different
between the LXT384 and the IDT82V2048. Bit 2 in the Global Control
Register (0F Hex) is named JACF bit in the LXT384, but the same bit is
named JABW in the IDT82V2048. This bit and the depth of the jitter
attenuator FIFO will affect the value of the jitter attenuator 3dB corner
frequency in the LXT384. But in the IDT82V2048, only the JABW bit will
affect the jitter attenuator 3dB corner frequency.
Table 4
describes the
details.
7.0 JAS PIN SELECTION
In hardware mode, the status of the JAS pin (Pin # 87 QFP or Pin #J11
BGA) determines where to put the Jitter Attenuator. The LXT384 is dif-
ferent from the IDT82V2048 on this point. (Refer to
Table 6
)
8.0 DEFAULT VALUE OF RS REGISTER (RESET
REGISTER, ADDRESS IS 0A HEX)
Writing to this register will set all registers to their default values. The
default value of the RS register in the LXT384 is "00 Hex". In the
IDT82V2048 it is "FF Hex".
6.0 LPn SETTING (LOOP-BACK SELECTION PIN)
In hardware mode, the status of LPn pin decides the loop back config-
uration of the corresponding port. For "No Loop back" setting, the
LXT384 and IDT82V2048 are different. ( Refer to
Table 5
)
Table 4. Jitter Attenuator 3dB Corner Frequency
LXT384
E1 jitter attenuator 3 dB corner
32 bit FIFO
frequency, host mode
64 bit FIFO
T1 jitter attenuator 3dB corner
frequency, host mode
Jitter attenuator 3dB corner
frequency, hardware mode
JACF=0
JACF=1
E1
T1
2.5 Hz
3.5 Hz
3 Hz
6 Hz
3.5 Hz
6 Hz
JACF does not affect
this figure
FIFO setting does not
affect this figure
JACF and FIFO do not
affect this figure
JABW=0
JABW=1
JABW=0
JABW=1
E1
T1
IDT82V2048
1.7 Hz
6.5 Hz
2.5Hz
5 Hz
1.7 Hz
2.5 Hz
FIFO setting does not
affect this figure
FIFO setting does not
affect this figure
JACF and FIFO do not
affect this figure
Table 5. LPn Setting
LXT384
No Loop back on Portn
LPn = Not connected
IDT82V2048
LPn = 0.5 * VDDIO
Table 6. JAS Pin Selection
JAS(IDT)/JASEL(LXT384)
L
H
High Z
VDDIO/2
JA Position in LXT384
Transmit Path
Receive Path
Disabled
Undetermined
JA Position in IDT82V2048
Transmit Path
Receive Path
Undetermined
Disabled
3
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
