HANBit
HDD64M72D18W
DDR SDRAM Module 512Mbyte (64Mx72bit), based on 32Mx8, 4Banks, 8K
Ref., with 184Pin-DIMM
Part No. HDD64M72D18W
GENERAL DESCRIPTION
The HDD64M72D18W is a 64M x 72 bit Double Data Rate(DDR) Synchronous Dynamic RAM high-density memory
module. The module consists of eighteen CMOS 32M x 8 bit with 4banks DDR SDRAMs in 66pin TSOP-II 400mil packages
and 2K EEPROM in 8-pin TSSOP package on a 184-pin glass-epoxy. Four 0.1uF decoupling capacitors are mounted on
the printed circuit board in parallel for each DDR SDRAM. The HDD64M72D18W is a DIMM( Dual in line Memory
Module) .Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible
on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allows the same device
to be useful for a variety of high bandwidth, high performance memory system applications. All module components may be
powered from a single 2.5V DC power supply and all inputs and outputs are SSTL_2 compatible.
FEATURES
•
Part Identification
HDD64M72D18W
–
10A :
HDD64M72D18W
–
13A :
HDD64M72D18W
–
13B :
100MHz (CL=2)
133MHz (CL=2)
133MHz (CL=2.5)
•
512MB(64Mx72) Unbuffered DDR DIMM based on 32Mx8 DDR SDRSM
•
2.5V
±
0.2V VDD and VDDQ power supply
•
Auto & self refresh capability (8K Cycles / 64ms)
•
All input and output are compatible with SSTL_2 interface
•
Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock
•
All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock
•
MRS cycle with address key programs
- Latency (Access from column address) : 2, 2.5
- Burst length : 2, 4, 8
- Data scramble : Sequential & Interleave
•
Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock
•
All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock
•
The used device is 8M x 8bit x 4Banks DDR SDRAM
URL : www.hbe.co.kr
REV 1.0 (August.2002)
1
HANBit Electronics Co.,Ltd
.
HANBit
PIN ASSIGNMENT
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
HDD64M72D18W
Front
VREF
DQ0
V
SS
DQ1
DQS0
DQ2
V
DD
DQ3
NC
/RESET
V
SS
DQ8
DQ9
DQS1
V
DDQ
CK1
/CK1
V
SS
DQ10
DQ11
CKE0
V
DDQ
DQ16
DQ17
DQS2
V
SS
A9
DQ18
A7
V
DDQ
DQ19
PIN
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Back
A5
DQ24
V
SS
DQ25
DQS3
A4
V
DD
DQ26
DQ27
A2
V
SS
A1
CB0
CB1
V
DD
DQS8
A0
CB2
V
SS
CB3
BA1
KEY
PIN
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Frontl
V
DDQ
/WE
DQ41
/CAS
V
SS
DQS5
DQ42
DQ43
V
DD
* /CS2
DQ48
DQ49
V
SS
CK2
/CK2
V
DDQ
DQS6
DQ50
DQ51
V
SS
VDDID
DQ56
DQ57
V
DD
DQS7
DQ58
DQ59
V
SS
NC
SDA
SCL
PIN
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
Back
V
SS
DQ4
DQ5
V
DDQ
DM0
DQ6
DQ7
V
SS
NC
NC
*A13
V
DDQ
DQ12
DQ13
DM1
V
DD
DQ14
DQ15
CKE1
V
DDQ
* BA2
DQ20
A12
V
SS
DQ21
A11
DM2
V
DD
DQ22
A8
DQ23
PIN
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
Front
V
SS
A6
DQ28
DQ29
V
DDQ
DM3
A3
DQ30
V
SS
DQ31
CB4
CB5
V
DDQ
CK0
/CK0
V
SS
DM8
A10
CB6
V
DDQ
CB7
KEY
PIN
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Back
/RAS
DQ45
V
DDQ
/CS0
/CS1
DM5
V
SS
DQ46
DQ47
* /CS3
V
DDQ
DQ52
DQ53
NC
V
DD
DM6
DQ54
DQ55
V
DDQ
NC
DQ60
DQ61
V
SS
DM7
DQ62
DQ63
V
DDQ
SA0
SA1
SA2
VDDSPD
53
54
55
56
57
58
59
60
61
DQ32
V
DDQ
DQ33
DQS4
DQ34
V
SS
BA0
DQ35
DQ40
145
146
147
148
149
150
151
152
153
V
SS
DQ36
DQ37
V
DD
DM4
DQ38
DQ39
V
SS
DQ44
*These pins should be NC in the system which does not support SPD
PIN
PIN DESCRIPTION
PIN
A0~A12
BA0~BA1
DQ0~DQ63
CB0~CB7
DQS0~DQS8
DM0~DM8
CK0~CK2,
/CK0~/CK2
CKE0~CKE1
/CS0~/CS1
/RAS
/CAS
URL : www.hbe.co.kr
REV 1.0 (August.2002)
PIN DESCRIPTION
Power supply(2.5V)
Power supply for DQs(2.5V)
Power supply for reference
Serial EEPROM Power supply(3.3)
Ground
Address in EEPROM
Serial data I/O
Serial clock
VDD identification flag
No connection
Address input
Bank Select Address
Data input/output
Check Bit
Data Strobe input/output
Data-in Mask
Clock input
Clock enable input
Chip Select input
Row Address strobe
Column Address strobe
2
VDD
VDDQ
VREF
VDDSPD
VSS
SA0~SA2
SDA
SCL
VDDID
NC
HANBit Electronics Co.,Ltd
.
HANBit
FUNCTIONAL BLOCK DIAGRAM
/CS1
/CS0
HDD64M72D18W
A12
A12
URL : www.hbe.co.kr
REV 1.0 (August.2002)
3
HANBit Electronics Co.,Ltd
.
HANBit
PIN FUNCTION DESCRIPTION
Pin
CK, /CK
Clock
Name
HDD64M72D18W
Input Function
CK and CK are differential clock inputs. All address and control input signals are
sam-pled on the positive edge of CK and negative edge of CK. Output (read) data
is referenced to both edges of CK. Internal clock signals are derived from CK/CK.
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device
input buffers and output drivers. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE
POWER-DOWN(row ACTIVE in any bank). CKE is synchronous for all functions
CKE
Clock Enable
except for disabling outputs, which is achieved asynchronously. Input buffers,
excluding CK, CK and CKE are disabled during power-down and self refresh
modes, providing low standby power. CKE will recognizean LVCMOS LOW level
prior to VREF being stable on power-up.
CS enables(registered LOW) and disables(registered HIGH) the command
decoder.
All commands are masked when CS is registered HIGH. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the
command code.
Row/column addresses are multiplexed on the same pins.
/CS
Chip Select
A0 ~ A12
Address
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9
BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-CHARGE
BA0 ~ BA1
Bank select address
command is being applied.
Latches row addresses on the positive going edge of the CLK with /RAS low.
/RAS
Row address strobe
Column address
Strobe
Write enable
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with /CAS low.
Enables column access.
Enables write operation and row precharge.
/CAS
/WE
Latches data in starting from /CAS, /WE active.
Output with read data, input with write data. Edge-aligned with read data, cen-
DQS0~8
Data Strobe
tered in write data. Used to capture write data.
DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH along with that input data during a WRITE access. DM is sampled
DM0~8
Input Data Mask
on both edges of DQS. DM pins include dummy loading internally, to matches the
DQ and DQS load-ing.
DQ0 ~ 63
CB0~CB7
VDDQ
VDD
VSS
VREF
VDDSPD
VDDID
Data input/output
Check Bit
Supply
Supply
Supply
Supply
Supply
Data inputs/outputs are multiplexed on the same pins.
Check Bit Input/Output pins
DQ Power Supply : +2.5V
±
0.2V.
Power Supply : +2.5V
±
0.2V (device specific).
DQ Ground.
SSTL_2 reference voltage.
Serial EEPROM Power Supply : 3.3v
VDD identification Flag
URL : www.hbe.co.kr
REV 1.0 (August.2002)
4
HANBit Electronics Co.,Ltd
.
HANBit
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Voltage on any pin relative to Vss
Voltage on V
DD
supply relative to Vss
Voltage on V
DDQ
supply relative to Vss
Storage temperature
Power dissipation
SYMBOL
V
IN
, V
OUT
V
DD
V
DDQ
T
STG
P
D
RATING
-0.5 ~ 3.6
-1.0 ~ 3.6
-0.5 ~ 3.6
-55 ~ +150
27
HDD64M72D18W
UNTE
V
V
V
°C
W
mA
Short circuit current
I
OS
50
No
tes:
Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to Vss = 0V, T
A
= 0 to 70°C) )
PARAMETER
Supply Voltage
I/O Supply Voltage
I/O Reference Voltage
SYMBOL
V
DD
V
DDQ
V
REF
MIN
2.3
2.3
V
DDQ
/2 - 50mA
MAX
2.7
2.7
V
DDQ
/2 +
50mA
I/O Termination Voltage(system)
Input High Voltage
Input Low Voltage
Input Voltage Level, CK and /CK inputs
Input Differential Voltage, CK and /CK inputs
Input crossing point Voltage, CK and /CK
inputs
Input leakage current
Output leakage current
Output High current (V
OUT
= 1.95V)
Output Low current (V
OUT
= 0.35V)
Notes :
1. Includes
±
25mV margin for DC offset on V
REF
, and a combined total of
±
50mV margin for all AC noise and DC
offset on V
REF
, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on V
REF
and
internal DRAM noise coupled to V
REF
, both of which may result in V
REF
noise. V
REF
should be de-coupled with an
inductance of
≤
3nH.
2. V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected to be set
equal to V
REF
, and must track variations in the DC level of V
REF
3. V
ID
is the magnitude of the difference between the input level on CK and the input level on CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the
pad in simulation. The AC and DC input specifications are relative to a V
REF
envelop that has been bandwidth limited
to 200MHZ.
5. The value of V
IX
is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of
the same.
6. These charactericteristics obey the SSTL-2 class II standards.
URL : www.hbe.co.kr
REV 1.0 (August.2002)
5
HANBit Electronics Co.,Ltd
.
UNIT
V
V
V
NOTE
1
V
TT
V
IH
(DC)
V
IL
(DC)
V
IN
(DC)
V
ID
(DC)
V
IX
(DC)
V
REF
–
0.04
V
REF
+ 0.15
-0.3
-0.3
0.3
1.15
V
REF
+ 0.04
V
REF
+ 0.3
V
REF
- 0.15
V
DDQ
+ 0.3
V
DDQ
+ 0.6
1.35
V
V
V
V
V
V
2
4
4
3
5
I
LI
I
OZ
I
OH
I
OL
-2
-5
-16.8
16.8
2
5
uA
uA
mA
mA
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