SN54AC00, SN74AC00
QUADRUPLE 2 INPUT POSITIVE NAND GATES
SCAS524E − AUGUST 1995 − REVISED OCTOBER 2003
D
2-V to 6-V V
CC
Operation
D
Inputs Accept Voltages to 6 V
D
Max t
pd
of 7 ns at 5 V
SN54AC00 . . . J OR W PACKAGE
SN74AC00 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
SN54AC00 . . . FK PACKAGE
(TOP VIEW)
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
4B
4A
4Y
3B
3A
3Y
1Y
NC
2A
NC
2B
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
1B
1A
NC
V
CC
4B
4A
NC
4Y
NC
3B
NC − No internal connection
ORDERABLE
PART NUMBER
SN74AC00N
SN74AC00D
SN74AC00DR
SN74AC00NSR
SN74AC00DBR
SN74AC00PW
SN74AC00PWR
SNJ54AC00J
SNJ54AC00W
SNJ54AC00FK
AC00
SNJ54AC00J
SNJ54AC00W
SNJ54AC00FK
AC00
AC00
AC00
Tube
Tube
Tape and reel
Tape and reel
Tape and reel
Tube
Tape and reel
Tube
Tube
Tube
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
Y
L
H
H
B
H
X
L
On products compliant to MIL PRF 38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
description/ordering information
The ‘AC00 devices contain four independent 2-input NAND gates. Each gate performs the Boolean function
of Y = A
S
B or Y = A + B in positive logic.
ORDERING INFORMATION
TA
PDIP − N
SOIC − D
−40 C 85°C
−40°C to 85 C
SOP − NS
SSOP − DB
TSSOP − PW
CDIP − J
−55 C 125°C
−55°C to 125 C
CFP − W
LCCC − FK
PACKAGE†
TOP-SIDE
MARKING
SN74AC00N
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
A
H
L
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
2Y
GND
NC
3Y
3A
1
SN54AC00, SN74AC00
QUADRUPLE 2 INPUT POSITIVE NAND GATES
SCAS524E − AUGUST 1995 − REVISED OCTOBER 2003
logic diagram (positive logic)
A
B
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
CC
+ 0.5 V
Output voltage range, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
CC
+ 0.5 V
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±200
mA
Package thermal impedance,
θ
JA
(see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54AC00
MIN
VCC
VIH
Supply voltage
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
VCC = 3 V
VIL
VI
VO
IOH
Low-level input voltage
Input voltage
Output voltage
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
VCC = 3 V
IOL
∆t
/∆v
Low-level output current
Input transition rise or fall rate
VCC = 4.5 V
VCC = 5.5 V
VCC = 4.5 V
VCC = 5.5 V
0
0
2
2.1
3.15
3.85
0.9
1.35
1.65
VCC
VCC
−12
−24
−24
12
24
24
8
0
0
MAX
6
SN74AC00
MIN
2
2.1
3.15
3.85
0.9
1.35
1.65
VCC
VCC
−12
−24
−24
12
24
24
8
ns / V
mA
mA
V
V
V
V
MAX
6
UNIT
V
High-level input voltage
High-level output current
TA
Operating free-air temperature
−55
125
−40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54AC00, SN74AC00
QUADRUPLE 2 INPUT POSITIVE NAND GATES
SCAS524E − AUGUST 1995 − REVISED OCTOBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
3V
IOH = −50
µA
IOH = −12 mA
IOH = −24 mA
IOH = −50 mA†
IOH = −75 mA†
IOL = 50
µA
IOL =12 mA
IOL = 24 mA
IOL = 50 mA†
IOL = 75 mA†
II
ICC
Ci
VI = VCC or GND
VI = VCC or GND,
IO = 0
4.5 V
5.5 V
3V
4.5 V
5.5 V
5.5 V
5.5 V
3V
4.5 V
5.5 V
3V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
±0.1
2
±1
40
VOL
0.002
0.001
0.001
0.1
0.1
0.1
0.36
0.36
0.36
0.1
0.1
0.1
0.5
0.5
0.5
1.65
1.65
±1
20
µA
µA
pF
VOH
TA = 25°C
MIN
TYP
MAX
2.9
4.4
5.4
2.56
3.86
4.86
SN54AC00
MIN
2.9
4.4
5.4
2.4
3.7
4.7
3.85
3.85
0.1
0.1
0.1
0.44
0.44
0.44
V
MAX
SN74AC00
MIN
2.9
4.4
5.4
2.46
3.76
4.76
V
MAX
UNIT
VI = VCC or GND
5V
2.6
† Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
±
0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
FROM
(INPUT)
A or B
TO
(OUTPUT)
Y
TA = 25°C
MIN
TYP
MAX
2
1.5
7
5.5
9.5
8
SN54AC00
MIN
1
1
MAX
11
9
SN74AC00
MIN
2
1
MAX
10
8.5
UNIT
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
±
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
FROM
(INPUT)
A or B
TO
(OUTPUT)
Y
TA = 25°C
MIN
TYP
MAX
1.5
1.5
6
4.5
8
6.5
SN54AC00
MIN
1
1
MAX
8.5
7
SN74AC00
MIN
1.5
1
MAX
8.5
7
UNIT
ns
operating characteristics, V
CC
= 5 V, T
A
= 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
CL = 50 pF,
f = 1 MHz
TYP
40
UNIT
pF
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
SN54AC00, SN74AC00
QUADRUPLE 2 INPUT POSITIVE NAND GATES
SCAS524E − AUGUST 1995 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
TEST
tPLH/tPHL
S1
Open
Input
(see Note B)
tPLH
In-Phase
Output
tPHL
Out-of-Phase
Output
LOAD CIRCUIT
50% VCC
50% VCC
VCC
50% VCC
50% VCC
0V
tPHL
VOH
50% VCC
VOL
tPLH
VOH
50% VCC
VOL
2
×
VCC
From Output
Under Test
CL = 50 pF
(see Note A)
500
Ω
S1
Open
500
Ω
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
≤
1 MHz, ZO = 50
Ω,
tr
≤
2.5 ns, tf
≤
2.5 ns.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
5962-87549012A
Status
(1)
Package Type Package Pins Package
Drawing
Qty
LCCC
FK
20
1
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C)
-55 to 125
Device Marking
(4/5)
Samples
ACTIVE
TBD
POST-PLATE
N / A for Pkg Type
5962-
87549012A
SNJ54
AC00FK
5962-8754901CA
SNJ54AC00J
5962-8754901DA
SNJ54AC00W
AC00
5962-8754901CA
5962-8754901DA
SN74AC00D
SN74AC00DBLE
SN74AC00DE4
SN74AC00DG4
SN74AC00DR
SN74AC00DRE4
SN74AC00DRG4
SN74AC00N
SN74AC00NE4
SN74AC00NSR
SN74AC00PW
SN74AC00PWE4
SN74AC00PWLE
SN74AC00PWR
ACTIVE
ACTIVE
ACTIVE
OBSOLETE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
OBSOLETE
ACTIVE
CDIP
CFP
SOIC
SSOP
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SO
TSSOP
TSSOP
TSSOP
TSSOP
J
W
D
DB
D
D
D
D
D
N
N
NS
PW
PW
PW
PW
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
1
1
50
TBD
TBD
Green (RoHS
& no Sb/Br)
TBD
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Pb-Free
(RoHS)
Pb-Free
(RoHS)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TBD
Green (RoHS
& no Sb/Br)
A42
A42
CU NIPDAU
Call TI
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Call TI
CU NIPDAU
N / A for Pkg Type
N / A for Pkg Type
Level-1-260C-UNLIM
Call TI
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Call TI
Level-1-260C-UNLIM
-55 to 125
-55 to 125
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
50
50
2500
2500
2500
25
25
2000
90
90
AC00
AC00
AC00
AC00
AC00
SN74AC00N
SN74AC00N
AC00
AC00
AC00
2000
AC00
Addendum-Page 1
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