F85226
F85226F/FG
LPC to ISA Bridge
Release Date: July, 2007
Revision: V0.25P
Fintek
Feature Integration Technology Inc.
F85226
F85226 Datasheet Revision History
Version
0.10P
0.20P
0.21P
0.22P
Date
2003/12/18
2003/12/23
2003/12/29
2004/5/30
Page
Revision History
Original version (Non Register Description)
Added register and application circuit
3
5
1
4
-
Removed PCI
5v
Item of pin descriptions
Revised the type description of pin 92 from IN
ts
to O
24
Revised features :
Fully ISA bridge support except bus
master (By conditions)
Revised ROMCS#/ROM_EN pin’s description
Revised register descriptions
Update application circuit
Added “Green Package” ordering information
Company readdress
0.23P
0.24P
0.25P
2004/8/17
2005/04/15
2007/7/5
37
34
-
Please note that all data and specifications are subject to change without notice. All the trade marks of products and
companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Customers using or selling these products for use
in such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from such
improper use or sales.
F85226
I
July, 2007
V0.25P
Fintek
Feature Integration Technology Inc.
F85226
Table of Contents
General Description.............................................................................................................. 1
Features ............................................................................................................................... 1
Key Specifications ................................................................................................................ 1
Block Diagram ...................................................................................................................... 2
Pin Configuration .................................................................................................................. 3
Pin Descriptions.................................................................................................................... 3
6.1 Power Pin ....................................................................................................................... 4
6.2 Power on strapping signal .............................................................................................. 4
6.3 LPC interface .................................................................................................................. 4
6.4 ISA interface ................................................................................................................... 5
7. Function Description ........................................................................................................... 10
7.1 LPC interface: ............................................................................................................... 10
7.1.1 IO/Memory Read and Write Cycles ........................................................................... 12
7.1.2 DMA Read and Write Cycles ..................................................................................... 12
7.1.3 Booting Memory Read and Write Cycles ................................................................... 12
7.2 Serialized Interrupt........................................................................................................ 13
7.3 LPC DMA...................................................................................................................... 14
8. Registers Description ......................................................................................................... 15
8.1 Entry Key. ..................................................................................................................... 15
8.2 Configuration and Control Register – Index 03h ........................................................... 15
8.3 GPIO1 Function Select Register – Index 04h ............................................................... 16
8.4 GPIO2 Function Select Register – Index 05h ............................................................... 17
8.5 System Clock Register – Index 06h.............................................................................. 17
8.6 System Power down Register – Index 10h ................................................................... 18
8.7 GPIO Port Define Register (Low byte)– Index 11h ....................................................... 18
8.8 GPIO Port Define Register (High byte)– Index 12h ...................................................... 19
8.9 Address Decoder Register (I) – Index 013h.................................................................. 19
8.10 Address Decoder Register (II) – Index 014h............................................................... 20
8.11 GPIO Input Control Register – Index 15h.................................................................... 20
8.12 GPIO Output Data Register – Index 16h..................................................................... 21
8.13 GPIO1x Input Register – Index 17h ............................................................................ 21
8.14 GPIO2 Input Control Register – Index 18h ................................................................. 22
8.15 GPIO2 Output Data Register – Index 19h................................................................... 22
8.16 GPIO2 Input Register – Index 1Ah ............................................................................. 23
8.17 LED & IRQIN Control Register – Index 1Bh ............................................................... 23
1.
2.
3.
4.
5.
6.
F85226
II
July, 2007
V0.25P
Fintek
8.18
8.19
8.20
8.21
8.22
8.23
8.24
8.25
8.26
8.27
8.28
8.29
8.30
8.31
8.32
8.33
8.34
8.35
8.36
8.37
8.38
8.39
8.40
8.41
8.42
8.43
8.44
8.45
8.46
8.47
8.48
8.49
8.50
8.51
8.52
8.53
8.54
Feature Integration Technology Inc.
F85226
Master Setting Register – Index 1Ch .......................................................................... 23
Master Setting Register – Index 1Dh .......................................................................... 24
Refresh Address Register (Low Byte) – Index 1Eh..................................................... 24
Refresh Address Register (High Byte) – Index 1Fh .................................................... 24
Address1 Decode Mask Register – Index 20h............................................................ 24
Address1 Decode Register (Low Byte) – Index 21h ................................................... 24
Address1 Decode Register (High Byte) – Index 22h .................................................. 25
Address2 Decode Mask Register – Index 23h............................................................ 25
Address2 Decode Register (Low Byte) – Index 24h ................................................... 25
Address2 Decode Register (High Byte) – Index 25h .................................................. 25
ROM1 Decoder Mask Low Byte Register – Index 0x28.............................................. 26
ROM Decoder Mask (High Byte) Register – Index 0x29............................................. 26
ROM Decoder Address (Low Byte) Register – Index 0x2A......................................... 26
ROM Decoder Address (High Byte) Register – Index 0x2B ........................................ 26
ROM2 Decoder Mask Low Byte Register – Index 0x2C ............................................. 27
ROM2 Decoder Mask (High Byte) Register – Index 0x2D .......................................... 27
ROM2 Decoder Address (Low Byte) Register – Index 0x2E....................................... 27
ROM2 Decoder Address (High Byte) Register – Index 0x2F ...................................... 27
ADDR3 Decoder Mask High Byte Register – Index 0x30 ........................................... 28
ADDR3 Decoder Address Low Byte Register – Index 0x31........................................ 28
ADDR3 Decoder Address High Byte Register – Index 0x32 ....................................... 28
ADDR4 Decoder Mask High Byte Register – Index 0x33 ........................................... 28
ADDR4 Decoder Address Low Byte Register – Index 0x34........................................ 29
ADDR4 Decoder Address High Byte Register – Index 0x35 ....................................... 29
KBC Decoder Mask Register – Index 0x36 ................................................................ 29
KBC Decoder Address Low Byte Register – Index 0x37 ............................................ 30
KBC Decoder Address High Byte Register – Index 0x38............................................ 30
MC Decoder Mask Register – Index 0x39 .................................................................. 30
MC Decoder Address Low Byte Register – Index 0x3A.............................................. 30
MC Decoder Address High Byte Register – Index 0x3B ............................................. 31
RTC Decoder Mask Register – Index 0x3C ................................................................ 31
RTC Decoder Address Low Byte Register – Index 0x3D ............................................ 31
RTC Decoder Address High Byte Register – Index 0x3E ........................................... 31
IOH Decoder Mask Register – Index 0x3F ................................................................. 32
IOH Decoder Address Low Byte Register – Index 0x40 ............................................. 32
IOH Decoder Address High Byte Register – Index 0x41............................................. 32
Edge Detector Status Register – Index 0x50 .............................................................. 32
F85226
III
July, 2007
V0.25P
Fintek
Feature Integration Technology Inc.
F85226
8.55 IRQ Wakeup Register (I) – Index 0x51 ....................................................................... 33
8.56 IRQ Wakeup Register (II) – Index 0x52 ...................................................................... 33
8.57 CHIPID (1) Register – Index 5Ah................................................................................ 33
8.58 CHIPID (2) Register – Index 5Bh................................................................................ 33
8.59 VERSION Register – Index 5Ch ................................................................................. 34
8.60 VENDOR ID (1) Register – Index 5Dh........................................................................ 34
8.61 VENDOR ID (2) Register – Index 5Eh ........................................................................ 34
9.
Ordering Information ......................................................................................................... 34
10.
Electrical characteristic .................................................................................................... 34
9.1 Absolute Maximum Ratings .......................................................................................... 34
9.2 DC Characteristics........................................................................................................ 35
11.
Package specification ...................................................................................................... 36
12.
Application Circuit ............................................................................................................ 37
F85226
IV
July, 2007
V0.25P
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