NC7SZ126 — TinyLogic
®
UHS Buffer with 3-STATE Output
March 2008
NC7SZ126
TinyLogic
®
UHS Buffer with 3-STATE Output
Features
■
Space saving SOT23 or SC70 5-lead package
■
Ultra small MicroPak™ leadless package
■
Ultra High Speed; t
PD
2.6ns Typ. into 50pF at 5V V
CC
■
High Output Drive; ±24mA at 3V V
CC
■
Broad V
CC
Operating Range; 1.65V to 5.5V
■
Matches the performance of LCX when operated at
General Description
The NC7SZ126 is a single buffer with 3-STATE output
from Fairchild's Ultra High Speed Series of TinyLogic
.
The device is fabricated with advanced CMOS technol-
ogy to achieve ultra high speed with high output drive
while maintaining low static power dissipation over a
very broad V
CC
operating range. The device is specified
to operate over the 1.65V to 5.5V range. The inputs and
output are high impedance above ground when V
CC
is
0V. Inputs tolerate voltages up to 6V independent of V
CC
operating voltage. The output tolerates voltages above
V
CC
in the 3-STATE condition.
3.3V V
CC
■
Power down high impedance inputs/output
■
Overvoltage tolerant inputs facilitate 5V to 3V
translation
■
Patented noise/EMI reduction circuitry implemented
Ordering Information
Order
Number
NC7SZ126M5X
NC7SZ126P5X
NC7SZ126L6X
Package
Number
MA05B
MAA05A
MAC06A
Product Code
Top Mark
7Z26
Z26
FF
Package Description
5-Lead SOT23, JEDEC MO-178,
1.6mm
5-Lead SC70, EIAJ SC-88a,
1.25mm Wide
6-Lead MicroPak, 1.0mm Wide
Supplied As
3k Units on Tape and Reel
3k Units on Tape and Reel
5k Units on Tape and Reel
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1996 Fairchild Semiconductor Corporation
NC7SZ126 Rev. 1.10.0
www.fairchildsemi.com
NC7SZ126 — TinyLogic
®
UHS Buffer with 3-STATE Output
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
V
IN
V
OUT
I
IK
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
@ V
IN
<
–0.5V
@ V
IN
> 6V
DC Output Diode Current
@ V
OUT
<
–0.5V
@ V
OUT
>
6V, V
CC
= GND
DC Output Current
DC V
CC
/GND Current
Storage Temperature
Parameter
Rating
–0.5V to +6V
–0.5V to +6V
–0.5V to +6V
–50mA
+20mA
–50mA
+20mA
±50mA
±50mA
-65°C to +150°C
150°C
260°C
200mW
150mW
I
OK
I
OUT
I
CC
/I
GND
T
STG
T
J
T
L
P
D
Junction Temperature under Bias
Junction Lead Temperature (Soldering, 10 seconds)
Power Dissipation @ +85°C
SOT23-5
SC70-5
Recommended Operating Conditions
(1)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
CC
V
IN
V
OUT
Supply Voltage Operation
Supply Voltage Data Retention
Input Voltage
Output Voltage
Active State
3-STATE
Operating Temperature
Input Rise and Fall Time
V
CC
= 1.8V, 2.5V ±0.2V
V
CC
= 3.3V ±0.3V
V
CC
= 5.0V ±0.5V
Thermal Resistance
SOT23-5
SC70-5
Parameter
Rating
1.65V to 5.5V
1.5V to 5.5V
0V to 5.5V
0V to V
CC
0V to 5.5V
–
40°C to +85°C
0ns/V to 20ns/V
0ns/V to 10ns/V
0ns/V to 5ns/V
300°C/W
425°C/W
T
A
t
r
, t
f
θ
JA
Notes:
1. Unused inputs must be held HIGH or LOW. They may not float.
©1996 Fairchild Semiconductor Corporation
NC7SZ126 Rev. 1.10.0
www.fairchildsemi.com
3
NC7SZ126 — TinyLogic
®
UHS Buffer with 3-STATE Output
AC Electrical Characteristics
T
A
=
+25°C
Symbol
t
PLH
, t
PHL
T
A
=
–40°C
to +85°C
2.0
2
0.8
0.5
0.5
1.5
0.8
2.0
2
1.5
1.5
0.8
2.0
2.0
1.0
1.0
0.5
13.8
11.5
8.0
5.5
4.8
6.0
5.3
15.6
12
8.5
6.0
5.3
14.5
12
8.5
6.0
5.0
pF
pF
pF
Figure 2
ns
Figure 1
Figure 3
ns
ns
Figure 1
Figure 3
Figure 1
Figure 3
ns
Figure 1
Figure 3
Parameter
Propagation
Delay
V
CC
(V)
1.65
1.8
2.5 ± 0.2
3.3 ± 0.3
5.0 ± 0.5
Conditions
C
L
=
15pF, RD
=
1MΩ,
S
1
=
OPEN
Min.
2.0
2
0.8
0.5
0.5
Typ. Max. Min. Max. Units Fig. No.
6.4
5.3
3.4
2.5
2.1
3.2
2.6
8.4
6.1
3.8
3.2
2.3
6.5
5.6
4.0
3.5
2.5
4
8
13.2
11
7.5
5.2
4.5
5.7
5.0
15.0
11.5
8.0
5.7
5.0
13.2
11
8.0
5.7
4.7
t
PLH
, t
PHL
Propagation
Delay
Output Enable
Time
3.3 ± 0.3
5.0 ± 0.5
1.65
1.8
2.5 ± 0.2
3.3 ± 0.3
5.0 ± 0.5
C
L
=
50pF, RD
=
500Ω,
S
1
=
OPEN
C
L
=
50pF, RD
=
500Ω,
RU
=
500Ω,
S
1
=
GND for t
PZH
,
S
1
=
V
I
for t
PZL
,
V
I
=
2
×
V
CC
C
L
=
50 pF, RD
=
500Ω,
RU
=
500Ω,
S
1
=
GND for t
PHZ
,
S
1
=
V
I
for t
PLZ
,
V
I
=
2
×
V
CC
1.5
0.8
2.0
2.0
1.5
1.5
0.8
2.0
2.0
1.0
1.0
0.5
t
PZL
, t
PZH
t
PLZ
, t
PHZ
Output Disable
Time
1.65
1.8
2.5 ± 0.2
3.3 ± 0.3
5.0 ± 0.5
C
IN
C
OUT
C
PD
Input
Capacitance
Output
Capacitance
Power Dissipation
Capacitance
0
0
3.3
5.0
(2)
17
24
Note:
2. C
PD
is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current
consumption (I
CCD
) at no output loading and operating at 50% duty cycle. (See Figure 2.) C
PD
is related to I
CCD
dynamic operating current by the expression: I
CCD
=
(C
PD
) (V
CC
) (f
IN
) + (I
CC
static).
©1996 Fairchild Semiconductor Corporation
NC7SZ126 Rev. 1.10.0
www.fairchildsemi.com
5
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