Data Path Interface (DPI) to
UTOPIA Level 1 Header
Translation Device
IDT77V012
SRAM
64K x 32
to
256K x 32
DPI
Receive
IDT77V012
UTOPIA 1
to DPI
interface w/
Header
Translation
IDT77V400
Switching
Memory
OC-3
or
STS-3
UTOPIA 1
Receive
IDT77155
PHY
UTOPIA 1
Transmit
Utility
Bus
"
"
"
"
Figure 1 Typical IDT77V012 Application with the IDT77V400 Switching Memory
1 of 46
2001 Integrated Device Technology, Inc.
QRLWSLUFVH'
DPI
Transmit
"
"
"
"
8, 12, 24, 28 or 32-bit ATM header lookup. Ideal for network
side of SwitchStar DSLAM designs where full header access
is needed
Supports VPI Tunneling
Supports both UNI and NNI formats
Accounting functionality counts the number of cells on a
per VC basis
8-bit UTOPIA Level 1 Tx and Rx interfaces
Supports UTOPIA Level 1 cell mode operation
4-bit DPI Tx and Rx interfaces
DPI interface supports cell sizes from 52 to 56 bytes for
applications requiring a TAG
DPI interface operates up to 66MHz
In-Stream™ (In-band) programming for configuration of the
77V012, PHY and external search SRAM
Supports up to 8K active connections with an external 128K
x 32 SRAM. Up to 16K connections are supported in a 256K
x 32 SRAM
Inserts new ATM cell header and up to four bytes of TAG in
receive direction, and removes TAG from cell header in
transmit direction
Utility bus interface for programming PHY devices
Single +3.3V ± 0.3V power supply required
Inputs are +5.0V tolerant
PDUJDL' NFRO%
PDUJDL' NFRO%
PDUJDL' NFRO%
PDUJDL' NFRO%
WVL/ VHUXWDH)
WVL/ VHUXWDH)
WVL/ VHUXWDH)
WVL/ VHUXWDH)
The IDT77V012 provides full header translation functionality along
with Data Path Interface (DPI) to UTOPIA Level 1 translation for switch
and DSLAM designs using the IDT SwitchStar. The address search and
replacement algorithm is performed using a VPI Tunneling or Full
Header format on 8, 12, 24, 28 or 32-bits of the header. This added flex-
ibility makes it suitable for both UNI and NNI formats. External memory
is required to perform the header translation (receive direction only),
which will support up to 16K connections using a 256K x 32 SRAM. The
new header, which is obtained as a result of the search, can be used to
overwrite the existing cell header in the receive path. A four byte TAG
can also be added to aid in routing cells.
The 77V012 also contains cell counters in the transmit and receive
direction. The counters can be used to provide detailed per VC
accounting information for a particular port.
Other features include In-Stream™ programming, which can be
utilized on either the DPI or UTOPIA interfaces, a Utility Bus interface for
accessing registers in the PHY device, and an interface for an
EEPROM.
5347drw01
March 26, 2001
DSC 5347/7
IDT77V012
INDEX
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
GND
RCLK
R xLED
RENB
GND
RCLAV
RxDATA[0]
RxDATA[1]
RxDATA[2]
VCC
RxDATA[3]
RxDATA[4]
RxDATA[5]
RxDATA[6]
RxDATA[7]
RSOC
TCLAV
VCC
GND
TCLK
TxLED
TENB
TxDATA[0]
TxDATA[1]
TxDATA[2]
TxDATA[3]
TxDATA[4]
GND
VCC
TxDATA[5]
TxDATA[6]
TxDATA[7]
TxPRTY
TSOC
CNTRL_A
VCC
VCC
DATA[10]
DATA[11]
DATA[12]
DATA[13]
DATA[14]
DATA[15]
ADDR[16]
GND
VCC
ADDR[15]
ADDR[14]
ADDR[13]
ADDR[12]
ADDR[11]
ADDR[10]
ADDR[9]
ADDR[8]
ADSP
OE
GW
SCLK
GND
VCC
ADDR[17]
CE
ADDR[0]
ADDR[1]
ADDR[2]
ADDR[3]
ADDR[4]
ADDR[5]
ADDR[6]
ADDR[7]
DATA[16]
GND
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
QRLWDUXJLIQR& QL3
QRLWDUXJLIQR& QL3
QRLWDUXJLIQR& QL3
QRLWDUXJLIQR& QL3
PDUJDL' NFRO%
PDUJDL' NFRO%
PDUJDL' NFRO%
PDUJDL' NFRO%
DPI
Transmit
Interface
TAG
Removal
UTOPIA 1
Transmit
Interface
Cell
Generator
Cell
Receiver
Utility Bus
Interface
EEPROM
Interface
DPI
Receive
Interface
TAG
Adder and
MUX
RxFIFO
UTOPIA 1
Receive
Interface
Search Tree
SRAM
Interface
5347drw02
GND
DTxDATA[0]
DTxDATA[1]
DTxDATA[2]
DTxDATA[3]
DTxFRM
VCC
GND
DTxCLK
DRxFRM
DRxDATA[0]
DRxDATA[1]
DRxDATA[2]
DRxDATA[3]
VCC
GND
DRxCLK
EECS
EEDIN
EEDOUT
EECLK
SYS RST
SYSCLK
GND
VCC
DATA[0]
DATA[1]
DATA[2]
DATA[3]
DATA[4]
DATA[5]
DATA[6]
DATA[7]
DATA[8]
DATA[9]
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
IDT77V012
PQFP
TOP
VIEW
(3)
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
GND
CNTRL_B
ALE
AD[7]
AD[6]
AD[5]
AD[4]
AD[3]
VCC
GND
AD[2]
AD[1]
AD[0]
PHYIN T
RD
WR
PH YR ST
PH Y C S
DATA[31]
DATA[30]
DATA[29]
DATA[28]
DATA[27]
DATA[26]
DATA[25]
DATA[24]
DATA[23]
GND
VCC
DATA[22]
DATA[21]
DATA[20]
DATA[19]
DATA[18]
DATA[17]
VCC
5347drw03
Note:
1. All power pins must be connected to a 3.3V ± 0.3V power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate orientation of the actual part-marking.
2 of 46
March 26, 2001
IDT77V012
DRxDATA [0]
DRxDATA [1]
DRxDATA [2]
DRxDATA [3]
DRxFRM
DRxCLK
DTxDATA [0]
DTxDATA [1]
DTxDATA [2]
DTxDATA [3]
DTxFRM
DTxCLK
RxDATA [0]
RxDATA [1]
RxDATA [2]
RxDATA [3]
RxDATA [4]
RxDATA [5]
RxDATA [6]
RxDATA [7]
RSOC
RCLAV
RENB
RxLED
RCLK
TxDATA [0]
TxDATA [1]
TxDATA [2]
TxDATA [3]
TxDATA [4]
TxDATA [5]
TxDATA [6]
TxDATA [7]
TSOC
11
12
13
14
10
17
2
3
4
5
6
9
138
137
136
134
133
132
131
130
129
139
141
142
143
122
121
120
119
118
115
114
113
111
O
O
O
O
O
I/O
I
I
I
I
I
O
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
O
O
O
O
4-bit output data bus used to transfer data to a DPI device [LSB].
4-bit output data bus used to transfer data to a DPI device [LSB+1].
4-bit output data bus used to transfer data to a DPI device [LSB+2].
4-bit output data bus used to transfer data to a DPI device [MSB].
DPI receive start of frame marker.
Receive DPI clock.
4-bit input data bus used to transfer data from a DPI device [LSB].
4-bit input data bus used to transfer data from a DPI device [LSB+1].
4-bit input data bus used to transfer data from a DPI device [LSB+2].
4-bit input data bus used to transfer data from a DPI device [MSB].
DPI transmit start of frame marker.
Transmit DPI clock.
8-bit UTOPIA 1 input data bus used to transfer data from a PHY device [LSB].
8-bit UTOPIA 1 input data bus used to transfer data from a PHY device [LSB+1].
8-bit UTOPIA 1 input data bus used to transfer data from a PHY device [LSB+2].
8-bit UTOPIA 1 input data bus used to transfer data from a PHY device [LSB+3].
8-bit UTOPIA 1 input data bus used to transfer data from a PHY device [LSB+4].
8-bit UTOPIA 1 input data bus used to transfer data from a PHY device [LSB+5].
8-bit UTOPIA 1 input data bus used to transfer data from a PHY device [LSB+6].
8-bit UTOPIA 1 input data bus used to transfer data from a PHY device [MSB].
UTOPIA 1 Receive Start of Cell.
UTOPIA 1 Receive Cell Available.
UTOPIA 1 Receive Enable.
UTOPIA 1 Receive LED, open drain.
UTOPIA 1 Receive Clock.
8-bit UTOPIA 1 output data bus used to transfer data to a PHY device [LSB].
8-bit UTOPIA 1 output data bus used to transfer data to a PHY device [LSB+1].
8-bit UTOPIA 1 output data bus used to transfer data to a PHY device [LSB+2].
8-bit UTOPIA 1 output data bus used to transfer data to a PHY device [LSB+3].
8-bit UTOPIA 1 output data bus used to transfer data to a PHY device [LSB+4].
8-bit UTOPIA 1 output data bus used to transfer data to a PHY device [LSB+5].
8-bit UTOPIA 1 output data bus used to transfer data to a PHY device [LSB+6].
8-bit UTOPIA 1 output data bus used to transfer data to a PHY device [MSB].
UTOPIA 1 Transmit Start of Cell.
Table 1 Pin Description (Part 1 of 4)
3 of 46
QRLWSLUFVH'
March 26, 2001
WXSWX2
WXSQ,
HOED7 QRLWSLUFVH' QL3
HOED7 QRLWSLUFVH' QL3
HOED7 QRLWSLUFVH' QL3
HOED7 QRLWSLUFVH' QL3
UHEPX1
QL3
HPD1
QL3
IDT77V012
TCLAV
TENB
TxLED
TCLK
TxPRTY
EECLK
EECS
EEDIN
EEDOUT
AD[0]
AD[1]
AD[2]
AD[3]
AD[4]
AD[5]
AD[6]
AD[7]
PHYCS
RD
WR
ALE
PHYRST
PHYINT
SYSRST
SYSCLK
CNTRL_A
CNTRL_B
SCLK
ADSP
GW
CE
OE
ADDR[0]
128
123
124
125
112
21
18
19
20
96
97
98
101
102
103
104
105
91
94
93
106
92
95
22
23
110
107
58
55
57
62
56
63
I
O
O
O
O
O
O
I
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
I
I
I
O
O
O
O
O
O
O
O
I
UTOPIA 1 Transmit Cell Available.
UTOPIA 1 Transmit Enable.
UTOPIA 1 Transmit LED, open drain.
UTOPIA 1 Transmit Clock.
Transmit Parity.
EEPROM Clock.
EEPROM Chip Select.
Serial input from the EEPROM.
Serial output to the EEPROM.
Utility Bus Address and Data Bus [LSB].
Utility Bus Address and Data Bus [LSB+1].
Utility Bus Address and Data Bus [LSB+2].
Utility Bus Address and Data Bus [LSB+3].
Utility Bus Address and Data Bus [LSB+4].
Utility Bus Address and Data Bus [LSB+5].
Utility Bus Address and Data Bus [LSB+6].
Utility Bus Address and Data Bus [MSB].
Utility Bus PHY Chip Select.
Utility Bus Read.
Utility Bus Write.
Utility Bus Address Latch Enable.
PHY Reset, open drain.
PHY Interrupt.
System Reset.
System Clock.
Control pin A.
Control pin B.
SRAM Clock.
SRAM Address Status Processor.
SRAM Global Write Enable.
SRAM Chip Enable.
SRAM Output Enable.
SRAM Address bus.
Tx TAG Size [0]. Number of bytes to remove from cell in transmit direction (LSB).
Table 1 Pin Description (Part 2 of 4)
4 of 46
QRLWSLUFVH'
March 26, 2001
WXSWX2
WXSQ,
UHEPX1
QL3
HPD1
Q L3
IDT77V012
ADDR[1]
64
O
I
SRAM Address bus.
Tx TAG Size [1]. Number of bytes to remove from cell in transmit direction (LSB+1).
SRAM Address bus.
Tx TAG Size [2]. Number of bytes to remove from cell in transmit direction (MSB).
SRAM Address bus.
"Tx TAG Location. Location of TAG in the transmit direction. "0" beginning of cell, "1" end of cell."
SRAM Address bus.
"Tx Add HEC. Add a HEC placeholder. "0" do not add placeholder, "1" add placeholder."
SRAM Address bus.
Rx TAG Size [0]. Number of bytes to add to cell in receive direction (LSB).
SRAM Address bus.
Rx TAG Size [1]. Number of bytes to add to cell in receive direction (LSB + 1).
SRAM Address bus.
Rx TAG Size [2]. Number of bytes to add to cell in receive direction (MSB).
SRAM Address bus.
"Rx Rem HEC. Remove HEC from the cell. "0" do not remove the HEC byte, "1" remove the HEC byte."
SRAM Address bus.
"DPI Mode. Selects DRxCLK direction. "0" switch mode (output), "1" normal mode (input)."
SRAM Address bus.
"In-Stream™ Direction. Selects the interface that the In-Stream™ cells will be filtered on. "0" transmit DPI inter-
face, "1" receive UTOPIA interface."
SRAM Address bus.
"Init from EEPROM. Selects whether first four bytes stored in EEPROM are to be written to In-Stream™ Cell
Header registers. "0" do not write value to registers, "1" write four byte value from EEPROM to In-Stream™ Cell
Header registers."
SRAM Address bus.
SRAM Address bus.
SRAM Address bus.
SRAM Address bus.
SRAM Address bus.
SRAM Address bus.
SRAM Data bus.
SRAM Data bus.
SRAM Data bus.
SRAM Data bus.
SRAM Data bus.
Table 1 Pin Description (Part 3 of 4)
ADDR[2]
65
O
I
ADDR[3]
66
O
I
ADDR[4]
67
O
I
ADDR[5]
68
O
I
ADDR[6]
69
O
I
ADDR[7]
70
O
I
ADDR[8]
54
O
I
ADDR[9]
53
O
I
ADDR[10]
52
O
I
ADDR[11]
51
O
I
ADDR[12]
ADDR[13]
ADDR[14]
ADDR[15]
ADDR[16]
ADDR[17]
DATA[0]
DATA[1]
DATA[2]
DATA[3]
DATA[4]
50
49
48
47
44
61
26
27
28
29
30
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
5 of 46
QRLWSLUFVH'
March 26, 2001
WXSWX2
WXSQ,
UHEPX1
QL3
HPD1
Q L3
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