CMS6416LAx-15Ex
Document Title
64M(4Mx16) Low Power SDRAM
Revision History
Revision
No.
0.0
0.1
Initial Draft
Correct typo.
Add Write Burst Mode description
Add commercial & extended temperature options
Add package dimension
Extend Vddmax limit for 2.5V product
Change IDD specifications
Add Pb & Halogen free package item
Change from manual TCSR to auto TCSR
Change IDD2N specifications
Change Setup/Hold time
Change I
DD
3p/Idd6 specification
Add H(Pb-Free & Halogen Free) descriptions
History
Draft date
Jun.25
th
, 2004
Aug.13
th
, 2004
Remark
Preliminary
Preliminary
0.2
0.3
0.4
Oct.6
th
, 2004
Oct.20
th
, 2004
Dec.6
th
, 2004
Preliminary
Preliminary
Preliminary
1.0
Jan.5
th
, 2005
Preliminary
1.1
1.2
1.3
Jan.10
th
, 2005
Feb, 2005
Nov. 1
st
, 2005
Final
Rev1.3, Nov. 2005
CMS6416LAx-15Ex
Features
- Functionality
- Standard SDRAM Functionality
- Programmable burst lengths : 1, 2, 4, 8, or full page
- JEDEC Compatibility
- Low Power Features
- Low voltage power supply : 1.8V
- Auto TCSR(Temperature Compensated Self Refresh)
- Partial Array Self Refresh power-saving mode
- Deep Power Down Mode
- Driver Strength Control
- Operating Temperature Ranges:
- Special (-10℃ to +60℃)
- Commercial (0℃ to +70℃)
- Extended (-25℃ to +85℃)
- Industrial (-40℃ to +85℃)
-
LVCMOS Compatible IO Interface
-
54ball FBGA with 0.8mm ball pitch
- CMS6416LAF : Normal
- CMS6416LAG : Pb-Free
- CMS6416LAH : Pb-Free & Halogen Free
Functional Description
The CMS6416LAx-xxxx family is high-performance CMOS
Dynamic RAMs (DRAM) organized as 4M x 16. These devices
feature advanced circuit design to provide ultra-low active current
and extremely low standby current.This is ideal for providing
More Battery Life in portable applications such as wireless
handsets. The device is compatible with the JEDEC standard
LP-SDRAM specifications.
Logic Block Diagram
CKE
CLK
/CS
/WE
/CAS
/RAS
Bank 3
Bank 2
Bank 1
Bank 0
Control
Logic
Refresh
Counter
Mode
Reg
Enhanced
Mode
Reg
Bank 0
Bank 0
Row
Memory
Row
Addr
Row
Array
Addr
Latch/
Add
Latch/
Decoder
Mux
4Kx4K
- CMS6432LBH : Pb-Free & Halogen Free
Decoder
LDQM -
UDQM
Data
Output
Reg
Sense Amp
Bank
Control
Logic
A0-A11
BA0-BA1
Addr
Reg
Column
Column
Decoder
Column
Decoder
Column
Decoder
Decoder
Write Drivers
DQM Mask
READ DATA
LATCH
DQ0 -
DQ15
Data
Output
Reg
Column
Address
Latch
Selection Guide
Voltage
Device
V
DD
CMS6416LAx-15Ex
1.65-1.95V
V
DDQ
100MHz
1.65-V
DD
83MHz
8ns
Frequency
Access Time(t
AC
)
CL=2
CL=3
7ns
20ns
20ns
20ns
20ns
t
RCD
t
RP
Rev1.3, Nov. 2005
CMS6416LAx-15Ex
Pin Description
Symbol
CLK
Type
Input
Description
Clock : CLK is driven by the system clock. All SDRAM input signals are sampled on the positive
edge of CLK. CLK also increments the internal burst counter and controls the output registers.
Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. Deactivating the
clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation(all banks idle),
ACTIVE POWER-DOWN(row active in any bank) or CLOCK SUSPEND operation(burst/access
in progress). CKE is synchronous except after the device enters power-down and self refresh
modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers,
including CLK, are disabled during power-down and self refresh modes, providing low standby
power. CKE may be tied HIGH.
Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when /CS is registered HIGH. /CS provides for external
bank selection on systems with multiple banks. /CS is considered part of the command code.
Command Inputs : /CAS, /RAS, and /WE (along with /CS) define the command being entered.
Input/Output Mask: L(U)DQM is sampled HIGH and is an input mask signal for write accesses
and an output enable signal for read accesses. Input data is masked during a WRITE cycle. The
output buffers are placed in a High-Z state (two-clock latency) when during a READ cycle.
LDQM corresponds to DQ0 – DQ7 and UDQM corresponds to DQ8–DQ15.
Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or
PRECHARGE command is being applied. These pins also provide the op-code during a LOAD
MODE REGISTER command.
Address Inputs: A0–A11 are sampled during the ACTIVE command (row-address A0–A11)
and READ/WRITE command (column-address A0–A7; with A10 defining auto precharge) to
select one location out of the memory array in the respective bank. A10 is sampled during a
PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank
selected by BA0, BA1 (A10 LOW). The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
Data Input/Output : Data bus
No Connect
DQ Power: Provide isolated power to DQs for improved noise immunity.
DQ Ground: Provide isolated ground to DQs for improved noise immunity.
Power Supply: Voltage dependent on option.
Ground.
CKE
Input
/CS
Input
/CAS, /RAS, /WE
Input
LDQM, UDQM
Input
BA0, BA1
Input
A0-A11
Input
DQ
NC
V
DDQ
V
SSQ
V
DD
V
SS
I/O
-
Supply
Supply
Supply
Supply
Rev1.3, Nov. 2005
单片机
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