DATASHEET
SERIAL ATA/FIBER CHANNEL CLOCK SYNTHESIZER
Description
The ICS426 was developed for serial ATA (SATA) and
fiber channel. It generates a high quality, high
frequency clock output from a low cost frequency
crystal or clock input.
Using Phase-Locked-Loop (PLL) techniques, the
device runs from a standard fundamental mode,
inexpensive crystal or clock input.
ICS426
Features
•
•
•
•
•
•
•
Packaged in 16 pin TSSOP
Input crystal or clock frequency of 25 MHz (typical)
Supports serial ATA Generation 1
Supports Fiber Channel
Duty cycle of 45/55
Operating voltage of 3.3V
Advanced, low power, CMOS process
Block Diagram
VDD
4
S0:S1
X1
Crystal
Oscillator
X2
25 MHz
Crystal or
Clock Input
PLL /Clock
Synthesis
Circuitry
CLK
Capacitors may be
required with a crystal input.
6
GND
OE
IDT™ / ICS™
SERIAL ATA/FIBER CHANNEL CLOCK SYNTHESIZER
1
ICS426
REV B 091102
ICS426
SERIAL ATA/FIBER CHANNEL CLOCK SYNTHESIZER
CLOCK SYNTHESIZER
Pin Assignment
X1/ICLK
VDD
VDD
GND
GND
S1
VDD
CLK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
X2
GND
GND
OE
GND
S0
VDD
GND
Clock Output Select Table (MHz)
S1
0
0
1
1
S0
0
1
0
1
Input
25
25
25
25
CLK Output
75
150
106.25
156.25
16 pin 173 mil (0.65 mm) TSSOP
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin
Name
X1/ICLK
VDD
VDD
GND
GND
S1
VDD
CLK
GND
VDD
S0
GND
OE
GND
GND
X2
Pin
Type
XI
Power
Power
Power
Power
Input
Power
Output
Power
Power
Input
Power
Input
Power
Pin Description
Crystal connection. Connect to a 25 MHz fundamental mode
crystal or clock input.
Connect to +3.3 V.
Connect to +3.3 V.
Connect to ground.
Connect to ground.
Select pin 1 determines CLK output based on table above. Internal
pull-up.
Connect to +3.3 V.
Clock output. Tri-state output when OE is low.
Connect to ground.
Connect to +3.3V.
Select pin 0 determines CLK output based on table above. Internal
pull-up.
Connect to ground.
Output Enable. All outputs are tri-stated when low. Internal pull-up.
Connect to ground.
Connect to ground.
Crystal connection. Connect to a 25 MHz fundamental mode
crystal or float for clock input.
Power
XO
IDT™ / ICS™
SERIAL ATA/FIBER CHANNEL CLOCK SYNTHESIZER
2
ICS426
REV B 091102
ICS426
SERIAL ATA/FIBER CHANNEL CLOCK SYNTHESIZER
CLOCK SYNTHESIZER
External Components
Decoupling Capacitor
As with any high performance mixed-signal IC, the
ICS426 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01µF must be connected
between each VDD and the PCB ground plane.
-18pF)*2. In this equation, C
L
= crystal load capacitance
in pF. Example: For a crystal with a 20 pF load
capacitance, each crystal capacitor would be 4 pF
[(20-18) x 2] = 20.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01µF decoupling capacitors should be
mounted on the component side of the board as close
to the VDD pins as possible. No vias should be used
between the decoupling capacitors and VDD pins. The
PCB trace to VDD pins should be kept as short as
possible, as should the PCB trace to the ground via.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
3) To minimize EMI the 33Ω series termination resistor,
if needed, should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed away
from the ICS426. This includes signal traces just
underneath the device, or on layers adjacent to the
ground plane layer used by the device.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω
.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors, if
needed, must be connected from each of the pins X1
and X2 to ground.
The value (in pF) of these crystal caps should equal (C
L
IDT™ / ICS™
SERIAL ATA/FIBER CHANNEL CLOCK SYNTHESIZER
3
ICS426
REV B 091102
ICS426
SERIAL ATA/FIBER CHANNEL CLOCK SYNTHESIZER
CLOCK SYNTHESIZER
Phase Noise Graph
25 MHz crystal input, 106.25 MHz CLK output.
Phase Noise 106.25 MHz
0
-20
-40
L(f) dBc
-60
-80
-100
-120
-140
1E+3
10E+3
100E+3
offset frequency
1E+6
10E+6
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS426. These ratings, which
are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
7V
-0.5V to VDD+0.5V
0 to +70° C
-65 to +150° C
175° C
260° C
Rating
IDT™ / ICS™
SERIAL ATA/FIBER CHANNEL CLOCK SYNTHESIZER
4
ICS426
REV B 091102
ICS426
SERIAL ATA/FIBER CHANNEL CLOCK SYNTHESIZER
CLOCK SYNTHESIZER
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
0
+3.13
+3.3
Typ.
Max.
+70
+3.46
Units
°
C
V
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature 0 to +70° C
Parameter
Operating Voltage
Supply Current
Input High Voltage
Input Low Voltage
Output High Voltage
Output High Voltage
Output Low Voltage
Short Circuit Current
On Chip Pull-up Resistor
Input Capacitance
Symbol
VDD
IDD
V
IH
V
IL
V
OH
V
OH
V
OL
I
OS
R
PU
C
IN
Conditions
No load
OE, S0, S1
OE, S0, S1
I
OH
= -4 mA
I
OH
= -12 mA
I
OL
= 12mA
CLK output
OE, S0, S1
OE, S0, S1
Min.
3.13
2
Typ.
3.3
22
Max.
3.47
Units
V
mA
V
0.8
VDD-0.4
2.4
0.4
±50
150
5
V
V
V
V
mA
kΩ
pF
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature 0 to +70° C
Parameter
Input Frequency
Output Clock Duty Cycle
Output Rise Time
Output Fall Time
Short Term Jitter
Long Term Jitter
Phase Noise
Symbol
F
IN
t
OR
t
OF
Conditions
Crystal or clock input
Measured at VDD/2, Note 1
0.8 to 2.0V, Note 1
2.0 to 0.8V, Note 1
peak to peak, Note 1
Measured over 1000 cycles;
peak to peak, Note 1
106.25M CLK, relative to carrier,
100 Hz offset
106.25M CLK, relative to carrier,
1kHz offset
106.25M CLK, relative to carrier,
10 kHz offset
106.25M CLK, relative to carrier,
100 kHz offset
Min.
45
Typ.
25
50
1
1
±70
170
-90
-115
-121
-116
Max.
55
Units
MHz
%
ns
ns
ps
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Note 1: Measured with 15 pF load.
IDT™ / ICS™
SERIAL ATA/FIBER CHANNEL CLOCK SYNTHESIZER
5
ICS426
REV B 091102
stm32/stm8
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