TVS Diode Array
For ESD and Latch-Up Protection
PROTECTION PRODUCTS
Description
The SMF series TVS arrays are designed to protect sen-
sitive electronics from damage or latch-up due to ESD
and other voltage-induced transient events. They are
designed for use in applications where board space is at
a premium. Each device will protect up to five lines. They
are unidirectional devices and may be used on lines where
the signal polarities are above ground.
TVS diodes are solid-state devices designed specifically
for transient suppression. They feature large cross-sec-
tional area junctions for conducting high transient cur-
rents. They offer desirable characteristics for board level
protection including fast response time, low operating
and clamping voltage, and no device degradation.
The SMF series devices may be used to meet the immu-
nity requirements of IEC 61000-4-2, level 4. The small
SC70 package makes them ideal for use in portable elec-
tronics such as cell phones, PDA’s, notebook comput-
ers, and digital cameras.
SMF05C
PRELIMINARY
Features
ESD protection for data lines to
IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact)
IEC 61000-4-4 (EFT) 40A (5/50ns)
Small package for use in portable electronics
Protects five I/O lines
Working voltage: 5V
Low leakage current
Low operating and clamping voltages
Solid-state silicon-avalanche technology
Mechanical Characteristics
EIAJ SC70-6L package
Molding compound flammability rating: UL 94V-0
Marking : Marking Code
Packaging : Tape and Reel per EIA 481
Applications
Cellular Handsets and Accessories
Cordless Phones
Personal Digital Assistants (PDA’s)
Notebooks and Handhelds
Portable Instrumentation
Digital Cameras
Peripherals
MP3 Players
Circuit Diagram
Schematic & PIN Configuration
1
3
4
5
6
1
2
3
6
5
4
2
Revision 08/04/04
1
SC70-6L (Top View)
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SMF05C
PROTECTION PRODUCTS
Absolute Maximum Rating
R ating
Peak Pulse Power (tp = 8/20
µ
s)
Peak Pulse Current (tp = 8/20
µ
s)
ESD per IEC 61000-4-2 (Air)
ESD per IEC 61000-4-2 (Contact)
Lead Soldering Temperature
Operating Temperature
Storage Temperature
Symbol
P
p k
I
P P
V
ESD
T
L
T
J
T
STG
Value
100
8
20
15
260 (10 seconds)
-55 to +125
-55 to +150
PRELIMINARY
Units
Watts
A
kV
o
C
C
C
o
o
Electrical Characteristics
SMF05C
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage
Clamping Voltage
Junction Capacitance
Symbol
V
RWM
V
BR
I
R
V
C
V
C
C
j
I
t
= 1mA
V
RWM
= 5V, T=25°C
I
PP
= 5A, t
p
= 8/20µs
I
PP
= 8A, t
p
= 8/20µs
V
R
= 0V, f = 1MHz
6
5
9.8
12.5
130
Conditions
Minimum
Typical
Maximum
5
Units
V
V
µA
V
V
pF
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SMF05C
PROTECTION PRODUCTS
Typical Characteristics
Non-Repetitive Peak Pulse Power vs. Pulse Time
10
Peak Pulse Power - P
pk
(kW)
PRELIMINARY
Power Derating Curve
110
100
90
% of Rated Power or I
PP
80
70
60
50
40
30
20
10
1
0.1
0.01
0.1
1
10
Pulse Duration - t
p
(µs)
100
1000
0
0
25
50
75
100
o
125
150
Ambient Temperature - T
A
( C)
Pulse Waveform
110
100
90
80
Percent of I
PP
70
60
50
40
30
20
10
0
0
5
10
15
Time (µs)
20
25
30
td = I
PP
/2
e
-t
Clamping Voltage vs. Peak Pulse Current
Waveform
Parameters:
tr = 8µs
td = 20µs
9
8
Clamping Voltage - V
C
(V)
7
6
5
4
3
2
1
0
0
2
4
6
8
10
Peak Pulse Current - I
PP
(A)
Waveform
Parameters:
tr = 8µs
td = 20µs
Capacitance vs. Reverse Voltage
140
120
Capacitance - C
j
(pF)
100
80
60
40
20
f = 1MHz
ESD Clamping Characteristics
(8kV Contact Discharge per IEC 61000-4-2)
0
0
1
2
3
4
5
6
Reverse Voltage - V
R
(V)
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SMF05C
PROTECTION PRODUCTS
Applications Information
Device Connection for Protection of Five Data Lines
The SMF05C is designed to protect up to five unidirec-
tional data lines. The device is connected as follows:
1. Unidirectional protection of five I/O lines is
achieved by connecting pins 1, 3, 4, 5 and 6 to the
data lines. Pin 2 is connected to ground. The
ground connection should be made directly to the
ground plane for best results. The path length is
kept as short as possible to reduce the effects of
parasitic inductance in the board traces.
Circuit Board Layout Recommendations for Suppres-
sion of ESD.
Good circuit board layout is critical for the suppression
of ESD induced transients. The following guidelines are
recommended:
Place the SMF05C near the input terminals or
connectors to restrict transient coupling.
Minimize the path length between the SMF05C and
the protected line.
Minimize all conductive loops including power and
ground loops.
The ESD transient return path to ground should be
kept as short as possible.
Never run critical signals near board edges.
Use ground planes whenever possible.
Matte Tin Lead Finish
Matte tin has become the industry standard lead-free
replacement for SnPb lead finishes. A matte tin finish
is composed of 100% tin solder with large grains.
Since the solder volume on the leads is small com-
pared to the solder paste volume that is placed on the
land pattern of the PCB, the reflow profile will be
determined by the requirements of the solder paste.
Therefore, these devices are compatible with both
lead-free and SnPb assembly techniques. In addition,
unlike other lead-free compositions, matte tin does not
have any added alloys that can cause degradation of
the solder joint.
2
1
PRELIMINARY
SMF05C Circuit Diagram
3
4
5
6
Protection of Five Unidirectional Lines
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SMF05C
PROTECTION PRODUCTS
Typical Applications
PRELIMINARY
2004 Semtech Corp.
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