SMDA05C-8 through SMDA24C-8
PROTECTION PRODUCTS
Description
The SMDAxxC-8 series of transient voltage suppres-
sors are designed to protect components which are
connected to data and transmission lines from voltage
surges caused by electrostatic discharge (ESD), electri-
cal fast transients (EFT), and lightning.
TVS diodes are characterized by their high surge
capability, low operating and clamping voltages, and
fast response time. This makes them ideal for use as
board level protection of sensitive semiconductor
components. The SMDAxxC-8 is designed to provide
transient suppression on multiple data lines and I/O
ports. The low profile SO-14 design allows the user to
protect up to eight data and I/O lines with one pack-
age. They are bidirectional device and may be used on
lines where the normal operating voltage is above and
below ground (i.e. -12V to +12V).
The SMDAxxC-8 TVS diode array will meet the surge
requirements of IEC 61000-4-2 (Formerly IEC 801-2),
Level 4, “Human Body Model” for air and contact
discharge.
Bidirectional TVS Array
for Protection of Eight Lines
Features
Transient protection for data lines to
IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact)
IEC 61000-4-4 (EFT) 40A (5/50ns)
IEC 61000-4-5 (Lightning) 12A (8/20µs)
Small SO-14 surface mount package
Protects eight I/O lines
Working voltages: 5V, 12V, 15V and 24V
Low leakage current
Low operating and clamping voltages
Solid-state silicon avalanche technology
Mechanical Characteristics
JEDEC SO-14 package
Molding compound flammability rating: UL 94V-0
Marking : Part Number, Logo, Date Code
Packaging : Tape and Reel per EIA 481
RoHS/WEEE Compliant
Applications
RS-232 and RS-422 Data Lines
Microprocessor Based Equipment
LAN/WAN Equipment
Set-Top Box
Notebooks, Desktops, and Servers
Portable Instrumentation
Peripherals
Serial and Parallel Ports
Circuit Diagram
Schematic & PIN Configuration
1
14
1 & 14
7&8
2
3
4
5
6
13
12
11
10
9
8
2
3 12 13
5 6
9 10
7
SO-14 (Top View)
Revision 04/12/05
1
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SMDA05C-8 through SMDA24C-8
PROTECTION PRODUCTS
Absolute Maximum Rating
R ating
Peak Pulse Power (t
p
= 8/20µs)
Lead Soldering Temperature
Operating Temperature
Storage Temperature
Symbol
P
p k
T
L
T
J
T
STG
Value
300
260 (10 sec.)
-55 to +125
-55 to +150
Units
Watts
°C
°C
°C
Electrical Characteristics
SMDA05C-8
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage
Peak Pulse Current
Junction Capacitance
Symbol
V
RWM
V
BR
I
R
V
C
I
P P
C
j
I
t
= 1mA
V
RWM
= 5V, T=25°C
I
PP
= 1A, t
p
= 8/20µs
t
p
= 8/20µs
Between I/O Pins and
Ground
V
R
= 0V, f = 1MHz
6
20
9.8
17
350
Conditions
Minimum
Typical
Maximum
5
Units
V
V
µA
V
A
pF
SMDA12C-8
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamp ing Voltage
Peak Pulse Current
Junction Cap acitance
Symbol
V
RWM
V
BR
I
R
V
C
I
P P
C
j
I
t
= 1mA
V
RWM
= 12V, T=25°C
I
PP
= 1A, t
p
= 8/20µs
t
p
= 8/20µs
Between I/O Pins and
Ground
V
R
= 0V, f = 1MHz
13.3
1
19
12
120
Conditions
Minimum
Typical
Maximum
12
Units
V
V
µA
V
A
pF
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SMDA05C-8 through SMDA24C-8
PROTECTION PRODUCTS
Electrical Characteristics
(Continued)
SMDA15C-8
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamp ing Voltage
Peak Pulse Current
Junction Cap acitance
Symbol
V
RWM
V
BR
I
R
V
C
I
P P
C
j
I
t
= 1mA
V
RWM
= 15V, T=25°C
I
PP
= 1A, t
p
= 8/20µs
t
p
= 8/20µs
Between I/O Pins and
Ground
V
R
= 0V, f = 1MHz
16.7
1
24
10
75
Conditions
Minimum
Typical
Maximum
15
Units
V
V
µA
V
A
pF
SMDA24C-8
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage
Peak Pulse Current
Junction Capacitance
Symbol
V
RWM
V
BR
I
R
V
C
I
P P
C
j
I
t
= 1mA
V
RWM
= 24V, T=25°C
I
PP
= 1A, t
p
= 8/20µs
t
p
= 8/20µs
Between I/O Pins and
Ground
V
R
= 0V, f = 1MHz
26.7
1
43
5
50
Conditions
Minimum
Typical
Maximum
24
Units
V
V
µA
V
A
pF
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SMDA05C-8 through SMDA24C-8
PROTECTION PRODUCTS
Typical Characteristics
Non-Repetitive Peak Pulse Power vs. Pulse Time
10
Peak Pulse Power - P
pk
(kW)
Power Derating Curve
110
100
90
% of Rated Power or I
PP
80
70
60
50
40
30
20
10
1
0.1
0.01
0.1
1
10
Pulse Duration - t
p
(µs)
100
1000
0
0
25
50
75
100
o
125
150
Ambient Temperature - T
A
( C)
Pulse Waveform
110
100
90
80
Percent of I
PP
70
60
50
40
30
20
10
0
0
5
10
15
Time (µs)
20
25
30
td = I
PP
/2
e
-t
Waveform
Parameters:
tr = 8µs
td = 20µs
ESD Pulse Waveform (IEC 61000-4-2)
Level
IEC 61000-4-2 Discharge Parameters
First
Peak
Current
(A )
1
2
3
4
7.5
15
22.5
30
Peak
Current
at 30 ns
(A )
4
8
12
16
Peak
Current
at 60 ns
(A )
8
4
6
8
Test
Test
Voltage
Voltage
(Contact
(A ir
Discharge) Discharge)
(kV)
(kV)
2
4
6
8
2
4
8
15
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SMDA05C-8 through SMDA24C-8
PROTECTION PRODUCTS
Applications Information
Device Connection for Protection of Eight Data Lines
The SMDAxxC-8 is designed to protect up to 8 data or
I/O lines. They are bidirectional devices and may be
used on lines where the signal polarities are above and
below ground.
The SMDAxxC-8 TVS arrays employ a monolithic struc-
ture. Therefore, the working voltage (V
RWM
) and break-
down voltage (V
BR
) specifications apply to the differen-
tial voltage between any two data line pins. For ex-
ample, the SMDA24C-8 is designed for a maximum
voltage excursion of ±12V between any two data lines.
The device is connected as follows:
Connection Diagram
Pins 2, 3, 5, 6, 9, 10, 12 and 13 are connected to
the lines that are to be protected. Pins 1, 7, 8,
and 14 are connected to ground. The ground
connections should be made directly to the ground
plane for best results. The path length is kept as
short as possible to reduce the effects of parasitic
inductance in the board traces. Pins 4 and 11 are
not connected.
Circuit Board Layout Recommendations for Suppres-
sion of ESD.
Good circuit board layout is critical for the suppression
of ESD induced transients. The following guidelines are
recommended:
Place the TVS near the input terminals or connec-
tors to restrict transient coupling.
Minimize the path length between the TVS and the
protected line.
Minimize all conductive loops including power and
ground loops.
The ESD transient return path to ground should be
kept as short as possible.
Never run critical signals near board edges.
Use ground planes whenever possible.
Matte Tin Lead Finish
Matte tin has become the industry standard lead-free
replacement for SnPb lead finishes. A matte tin finish
is composed of 100% tin solder with large grains.
Since the solder volume on the leads is small com-
pared to the solder paste volume that is placed on the
land pattern of the PCB, the reflow profile will be
determined by the requirements of the solder paste.
Therefore, these devices are compatible with both
lead-free and SnPb assembly techniques. In addition,
unlike other lead-free compositions, matte tin does not
have any added alloys that can cause degradation of
the solder joint.
Circuit Diagram
GND
1
I/O 1
I/O 2
N.C.
I/O 3
I/O 4
2
14
GND
I/O 8
I/O 7
N.C.
I/O 6
I/O 5
GND
13
3
12
4
11
5
10
6
9
GND
7
8
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