Unidirectional TVS Array
for Protection of Six Lines
PROTECTION PRODUCTS
Description
The SMDA series of transient voltage suppressors are
designed to protect components which are connected
to data and transmission lines from voltage surges
caused by electrostatic discharge (ESD), electrical fast
transients (EFT), and lightning.
TVS diodes are characterized by their high surge
capability, low operating and clamping voltages, and
fast response time. This makes them ideal for use as
board level protection of sensitive semiconductor
components. The SMDA05-6 is designed to provide
transient suppression on multiple data lines and I/O
ports. It is designed to operate on 5V digital lines. The
low profile SO-8 design allows the user to protect up to
six data and I/O lines with one package.
The SMDA05-6 TVS diode array will meet the surge
requirements of IEC 61000-4-2 (Formerly IEC 801-2),
Level 4, “Human Body Model” for air and contact
discharge.
SMDA05-6
Features
300 watts peak pulse power (tp = 8/20µs)
Transient protection for data lines to
IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact)
IEC 61000-4-4 (EFT) 40A (5/50ns)
IEC 61000-4-5 (Lightning) 12A (8/20µs)
Protects up to 6 unidirectional lines
Low operating voltage
Low clamping voltage
Solid-state silicon avalanche technology
Mechanical Characteristics
JEDEC SO-8 package
UL 497B listed
Molding compound flammability rating: UL 94V-0
Marking : Part number, date code, logo
Packaging : Tube or Tape and Reel per EIA 481
RoHS/WEEE Compliant
Applications
5V data and I/O lines
Communication lines
Microprocessor based equipment
LAN/WAN equipment
Servers
Notebook and Desktop PC
Instrumentation
Peripherals
Circuit Diagram
Schematic & PIN Configuration
SO-8 (Top View)
Revision 08/15/06
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SMDA05-6
PROTECTION PRODUCTS
Absolute Maximum Rating
R ating
Peak Pulse Power (t
p
= 8/20µs)
Peak Pulse Current (t
p
= 8/20µs)
Lead Soldering Temperature
Operating Temperature
Storage Temperature
Symbol
P
p k
I
P P
T
L
T
J
T
STG
Value
300
17
260 (10 sec.)
-55 to +125
-55 to +150
Units
Watts
A
°C
°C
°C
Electrical Characteristics
SMDA05-6
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage
Clamping Voltage
Junction Capacitance
Symbol
V
RWM
V
BR
I
R
V
C
V
C
C
j
I
t
= 1mA
V
RWM
= 5V, T=25°C
I
PP
= 1A, t
p
= 8/20µs
I
PP
= 5A, t
p
= 8/20µs
Between I/O pins and
Ground
V
R
= 0V, f = 1MHz
6
20
9.8
11
400
Conditions
Minimum
Typical
Maximum
5
Units
V
V
µA
V
V
pF
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SMDA05-6
PROTECTION PRODUCTS
Typical Characteristics
Non-Repetitive Peak Pulse Power vs. Pulse Time
10
Peak Pulse Power - P
pk
(kW)
Power Derating Curve
110
100
90
% of Rated Power or I
PP
80
70
60
50
40
30
20
10
1
0.1
0.01
0.1
1
10
Pulse Duration - t
p
(µs)
100
1000
0
0
25
50
75
100
o
125
150
Ambient Temperature - T
A
( C)
Pulse Waveform
110
100
90
80
Percent of I
PP
70
60
50
40
30
20
10
0
0
5
10
15
T im e (µs)
20
25
30
td = I
PP
/2
e
-t
W aveform
Parameters:
tr = 8µs
td = 20µs
Clamping Voltage vs. Peak Pulse Current
11
10
Clamping Voltage - V
C
(V)
9
8
7
6
5
4
3
2
1
0
0
2
4
6
8
10
12
14
16
18
Peak Pulse Current - I
PP
(A)
Waveform
Parameters:
tr = 8µs
td = 20µs
ESD Pulse Waveform (IEC 61000-4-2)
Level
IEC 61000-4-2 Discharge Parameters
First
Peak
Current
(A )
1
2
3
4
7.5
15
22.5
30
Peak
Current
at 30 ns
(A )
4
8
12
16
Peak
Current
at 60 ns
(A )
8
4
6
8
Test
Test
Voltage
Voltage
(Contact
(A ir
Discharge) Discharge)
(kV)
(kV)
2
4
6
8
2
4
8
15
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SMDA05-6
PROTECTION PRODUCTS
Applications Information
Device Connection for Protection of Six Data Lines
The SMDA05-6 is designed to protect up to 6 data or
I/O lines operating at 5 volts. They are unidirectional
devices and may be used on lines where the signal
polarities are above ground (i.e. 0 to 5V).
The device is connected as follows:
Pins 1, 2, 3, 4, 5 and 8 are connected to the lines
that are to be protected. Pins 6 and 7 are con-
nected to ground. The ground connections should
be made directly to the ground plane for best
results. The path length is kept as short as pos-
sible to reduce the effects of parasitic inductance
in the board traces.
Connection Diagram
Circuit Board Layout Recommendations for Suppres-
sion of ESD.
Good circuit board layout is critical for the suppression
of ESD induced transients. The following guidelines are
recommended:
Place the TVS near the input terminals or connec-
tors to restrict transient coupling.
Minimize the path length between the TVS and the
protected line.
Minimize all conductive loops including power and
ground loops.
The ESD transient return path to ground should be
kept as short as possible.
Never run critical signals near board edges.
Use ground planes whenever possible.
Matte Tin Lead Finish
Matte tin has become the industry standard lead-free
replacement for SnPb lead finishes. A matte tin finish
is composed of 100% tin solder with large grains.
Since the solder volume on the leads is small com-
pared to the solder paste volume that is placed on the
land pattern of the PCB, the reflow profile will be
determined by the requirements of the solder paste.
Therefore, these devices are compatible with both
lead-free and SnPb assembly techniques. In addition,
unlike other lead-free compositions, matte tin does not
have any added alloys that can cause degradation of
the solder joint.
DATA IN
DATA OUT
8
7
6
5
DATA IN
DATA OUT
Circuit Diagram
1
2
3
4
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SMDA05-6
PROTECTION PRODUCTS
Outline Drawing - SO-8
A
N
2X E/2
E1 E
1
ccc C
2X N/2 TIPS
2
e/2
B
D
aaa C
SEATING
PLANE
A2 A
C
bxN
bbb
A1
C A-B D
SIDE VIEW
GAGE
PLANE
0.25
e
D
h
h
H
DIMENSIONS
INCHES
MILLIMETERS
DIM
MIN NOM MAX MIN NOM MAX
c
A
A1
A2
b
c
D
E1
E
e
h
L
L1
N
01
aaa
bbb
ccc
-
.053
.069
-
.004
.010
-
.049
.065
-
.012
.020
-
.010
.007
.189 .193 .197
.150 .154 .157
.236 BSC
.050 BSC
-
.010
.020
.016 .028 .041
(.041)
8
-
8°
0°
.004
.010
.008
-
1.75
1.35
-
0.10
0.25
-
1.25
1.65
-
0.31
0.51
-
0.17
0.25
4.80 4.90 5.00
3.80 3.90 4.00
6.00 BSC
1.27 BSC
-
0.25
0.50
0.40 0.72 1.04
(1.04)
8
-
0°
8°
0.10
0.25
0.20
L
(L1)
DETAIL
01
A
SEE DETAIL
A
NOTES:
1.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H-
3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
4. REFERENCE JEDEC STD MS-012, VARIATION AA.
Land Pattern - SO-8
X
DIM
(C)
G
Z
C
G
P
X
Y
Z
DIMENSIONS
INCHES
MILLIMETERS
(.205)
.118
.050
.024
.087
.291
(5.20)
3.00
1.27
0.60
2.20
7.40
Y
P
NOTES:
1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
2. REFERENCE IPC-SM-782A, RLP NO. 300A.
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