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COP8CBR9/COP8CCR9/COP8CDR9 8-Bit CMOS Flash Based Microcontroller with 32k Memory,
Virtual EEPROM, 10-Bit A/D and Brownout
August 2003
COP8CBR9/COP8CCR9/COP8CDR9
8-Bit CMOS Flash Microcontroller with 32k Memory,
Virtual EEPROM, 10-Bit A/D and Brownout
1.0 General Description
The COP8CBR/CCR/CDR9 Flash microcontrollers are
highly integrated COP8
™
Feature core devices, with 32k
Flash memory and advanced features including Virtual EE-
PROM, A/D, High Speed Timers, USART, and Brownout
Reset. This single-chip CMOS device is suited for applica-
Device included in this datasheet:
Device
Flash Program
Memory
(bytes)
32k
RAM
(bytes)
Brownout
Voltage
I/O
Pins
37,39,49,
59
37,39,49,
59
37,39,49,
59
Packages
44 LLP,
44/68 PLCC,
48/56 TSSOP
44 LLP,
44/68 PLCC,
48/56 TSSOP
44 LLP,
44/68 PLCC,
48/56 TSSOP
Temperature
tions requiring a full featured, in-system reprogrammable
controller with large memory and low EMI. The same device
is used for development, pre-production and volume produc-
tion with a range of COP8 software and hardware develop-
ment tools.
COP8CBR9
1k
2.7V to 2.9V
−40˚C to +85˚C
COP8CCR9
32k
1k
4.17V to 4.5V
−40˚C to +85˚C
−40˚C to +125˚C
−40˚C to +85˚C
−40˚C to +125˚C
COP8CDR9
32k
1k
No Brownout
2.0 Features
KEY FEATURES
n
32 kbytes Flash Program Memory with Security Feature
n
Virtual EEPROM using Flash Program Memory
n
1 kbyte volatile RAM
n
10-bit Successive Approximation Analog to Digital
Converter (up to 16 channels)
n
100% Precise Analog Emulation
n
USART with onchip baud generator
n
2.7V – 5.5V In-System Programmability of Flash
n
High endurance -100k Read/Write Cycles
n
Superior Data Retention - 100 years
n
Dual Clock Operation with HALT/IDLE Power Save
Modes
n
Three 16-bit timers:
— Timers T2 and T3 can operate at high speed (50 ns
resolution)
— Processor Independent PWM mode
— External Event counter mode
— Input Capture mode
n
Brown-out Reset (COP8CBR9/CCR9)
OTHER FEATURES
n
Single supply operation:
— 2.7V–5.5V (−40˚C to +85˚C)
— 4.5V–5.5V (−40˚C to +125˚C)
n
Quiet Design (low radiated emissions)
n
Multi-Input Wake-up with optional interrupts
n
MICROWIRE/PLUS (Serial Peripheral Interface
Compatible)
n
Clock Doubler for 20 MHz operation from 10 MHz
Oscillator, with 0.5 µs Instruction Cycle
n
Thirteen multi-source vectored interrupts servicing:
— External Interrupt
— USART (2)
— Idle Timer T0
— Three Timers (each with 2 interrupts)
— MICROWIRE/PLUS Serial peripheral interface
— Multi-Input Wake-up
— Software Trap
n
Idle Timer with programmable interrupt interval
n
8-bit Stack Pointer SP (stack in RAM)
n
Two 8-bit Register Indirect Data Memory Pointers
n
True bit manipulation
n
WATCHDOG and Clock Monitor logic
n
Software selectable I/O options
— TRI-STATE
®
Output/High Impedance Input
— Push-Pull Output
— Weak Pull Up Input
n
Schmitt trigger inputs on I/O ports
n
High Current I/Os
n
Temperature range: –40˚C to +85˚C and –40˚C to
+125˚C (COP8CCR9/CDR9)
n
Packaging: 44 and 68 PLCC, 44 LLP, 48 and 56 TSSOP
n
True In-System, real time emulation and debug tools
available
COP8
™
is a trademark of National Semiconductor Corporation.
© 2003 National Semiconductor Corporation
DS101374
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COP8CBR9/COP8CCR9/COP8CDR9
3.0 Block Diagram
10137401
4.0 Ordering Information
Part Numbering Scheme
COP8
CB
Family and
Feature Set
Indicator
CB = Low Brownout Voltage
CC = High Brownout Voltage
CD = No Brownout
R
Program
Memory
Size
R = 32k
9
Program
Memory
Type
9 = Flash
H
No. Of Pins
H = 44 Pin
I = 48 Pin
k = 56 Pin
L = 68 Pin
VA
Package
Type
LQ = LLP
MT = TSSOP
VA = PLCC
8
Temperature
7 = -40 to +125˚C
8 = -40 to +85˚C
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2
COP8CBR9/COP8CCR9/COP8CDR9
Table of Contents
1.0 General Description ..................................................................................................................................... 1
2.0 Features ....................................................................................................................................................... 1
3.0 Block Diagram .............................................................................................................................................. 2
4.0 Ordering Information .................................................................................................................................... 2
5.0 Connection Diagrams ................................................................................................................................... 6
6.0 Architectural Overview ............................................................................................................................... 10
6.1 EMI REDUCTION .................................................................................................................................... 10
6.2 IN-SYSTEM PROGRAMMING AND VIRTUAL EEPROM ...................................................................... 10
6.3 DUAL CLOCK AND CLOCK DOUBLER ................................................................................................. 10
6.4 TRUE IN-SYSTEM EMULATION ............................................................................................................ 10
6.5 ARCHITECTURE ................................................................................................................................... 10
6.6 INSTRUCTION SET ............................................................................................................................... 10
6.6.1 Key Instruction Set Features ............................................................................................................. 10
6.6.2 Single Byte/Single Cycle Code Execution ....................................................................................... 10
6.6.3 Many Single-Byte, Multi-Function Instructions .................................................................................. 10
6.6.4 Bit-Level Control ................................................................................................................................ 11
6.6.5 Register Set ....................................................................................................................................... 11
6.7 PACKAGING/PIN EFFICIENCY .............................................................................................................. 11
7.0 Absolute Maximum Ratings ....................................................................................................................... 12
8.0 Electrical Characteristics ............................................................................................................................ 12
9.0 Pin Descriptions ......................................................................................................................................... 18
9.1 EMULATION CONNECTION ................................................................................................................... 20
10.0 Functional Description .............................................................................................................................. 20
10.1 CPU REGISTERS ................................................................................................................................. 20
10.2 PROGRAM MEMORY ........................................................................................................................... 20
10.3 DATA MEMORY .................................................................................................................................... 20
10.4 DATA MEMORY SEGMENT RAM EXTENSION .................................................................................. 21
10.4.1 Virtual EEPROM .............................................................................................................................. 22
10.5 OPTION REGISTER ............................................................................................................................. 22
10.6 SECURITY ............................................................................................................................................ 23
10.7 RESET ................................................................................................................................................... 23
10.7.1 External Reset ................................................................................................................................. 24
10.7.2 On-Chip Brownout Reset ................................................................................................................. 24
10.8 OSCILLATOR CIRCUITS ...................................................................................................................... 26
10.8.1 Oscillator .......................................................................................................................................... 26
................................................................................................................................................................... 0
10.8.2 Clock Doubler .................................................................................................................................. 27
10.9 CONTROL REGISTERS ....................................................................................................................... 27
10.9.1 CNTRL Register (Address X'00EE) ................................................................................................. 27
10.9.2 PSW Register (Address X'00EF) ..................................................................................................... 27
10.9.3 ICNTRL Register (Address X'00E8) ................................................................................................ 27
10.9.4 T2CNTRL Register (Address X'00C6) ............................................................................................. 27
10.9.5 T3CNTRL Register (Address X'00B6) ............................................................................................. 27
10.9.6 HSTCR Register (Address X'00AF) ................................................................................................ 28
10.9.7 ITMR Register (Address X'00CF) .................................................................................................... 28
10.9.8 ENAD Register (Address X'00CB) .................................................................................................. 28
11.0 In-System Programming ........................................................................................................................... 28
11.1 INTRODUCTION ................................................................................................................................... 28
11.2 FUNCTIONAL DESCRIPTION .............................................................................................................. 28
11.3 REGISTERS .......................................................................................................................................... 29
11.3.1 ISP Address Registers ..................................................................................................................... 29
11.3.2 ISP Read Data Register .................................................................................................................. 29
11.3.3 ISP Write Data Register ................................................................................................................... 29
11.3.4 ISP Write Timing Register ................................................................................................................ 29
11.4 MANEUVERING BACK AND FORTH BETWEEN FLASH MEMORY AND BOOT ROM ..................... 30
11.5 FORCED EXECUTION FROM BOOT ROM ......................................................................................... 30
11.6 RETURN TO FLASH MEMORY WITHOUT HARDWARE RESET ....................................................... 31
11.7 MICROWIRE/PLUS ISP ........................................................................................................................ 31
11.8 USER ISP AND VIRTUAL E
2
................................................................................................................ 32
11.9 RESTRICTIONS ON SOFTWARE WHEN CALLING ISP ROUTINES IN BOOT ROM ....................... 34
11.10 FLASH MEMORY DURABILITY CONSIDERATIONS ........................................................................ 34
12.0 Timers ....................................................................................................................................................... 35
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COP8CBR9/COP8CCR9/COP8CDR9
Table of Contents
(Continued)
12.1 TIMER T0 (IDLE TIMER) ......................................................................................................................
12.1.1 ITMR Register ..................................................................................................................................
12.2 TIMER T1, TIMER T2, AND TIMER T3 ................................................................................................
12.2.1 Timer Operating Speeds ..................................................................................................................
12.2.2 Mode 1. Processor Independent PWM Mode .................................................................................
12.2.3 Mode 2. External Event Counter Mode ...........................................................................................
12.2.4 Mode 3. Input Capture Mode ..........................................................................................................
12.3 TIMER CONTROL FLAGS ....................................................................................................................
13.0 Power Saving Features ............................................................................................................................
13.1 POWER SAVE MODE CONTROL REGISTER ....................................................................................
13.2 OSCILLATOR STABILIZATION .............................................................................................................
13.3 HIGH SPEED MODE OPERATION ......................................................................................................
13.3.1 High Speed Halt Mode ....................................................................................................................
13.3.1.1 Entering The High Speed Halt Mode .........................................................................................
13.3.1.2 Exiting The High Speed Halt Mode ...........................................................................................
13.3.1.3 HALT Exit Using Reset ..............................................................................................................
13.3.1.4 HALT Exit Using Multi-Input Wake-up .......................................................................................
13.3.1.5 Options .......................................................................................................................................
13.3.2 High Speed Idle Mode .....................................................................................................................
13.4 DUAL CLOCK MODE OPERATION ......................................................................................................
13.4.1 Dual Clock HALT Mode ...................................................................................................................
13.4.1.1 Entering The Dual Clock Halt Mode ..........................................................................................
13.4.1.2 Exiting The Dual Clock Halt Mode .............................................................................................
13.4.1.3 HALT Exit Using Reset ..............................................................................................................
13.4.1.4 HALT Exit Using Multi-Input Wake-up .......................................................................................
13.4.1.5 Options .......................................................................................................................................
13.4.2 Dual Clock Idle Mode ......................................................................................................................
13.5 LOW SPEED MODE OPERATION .......................................................................................................
13.5.1 Low Speed HALT Mode ...................................................................................................................
13.5.1.1 Entering The Low Speed Halt Mode .........................................................................................
13.5.1.2 Exiting The Low Speed Halt Mode ............................................................................................
13.5.1.3 HALT Exit Using Reset ..............................................................................................................
13.5.1.4 HALT Exit Using Multi-Input Wake-up .......................................................................................
13.5.1.5 Options .......................................................................................................................................
13.5.2 Low Speed Idle Mode ......................................................................................................................
13.6 MULTI-INPUT WAKE-UP ......................................................................................................................
14.0 USART .....................................................................................................................................................
14.1 USART CONTROL AND STATUS REGISTERS ...................................................................................
14.2 DESCRIPTION OF USART REGISTER BITS ......................................................................................
14.3 ASSOCIATED I/O PINS ........................................................................................................................
14.4 USART OPERATION ............................................................................................................................
14.4.1 Asynchronous Mode ........................................................................................................................
14.4.2 Synchronous Mode ..........................................................................................................................
14.5 FRAMING FORMATS ............................................................................................................................
14.6 USART INTERRUPTS ..........................................................................................................................
14.7 BAUD CLOCK GENERATION ..............................................................................................................
14.8 EFFECT OF HALT/IDLE .......................................................................................................................
14.9 DIAGNOSTIC ........................................................................................................................................
14.10 ATTENTION MODE .............................................................................................................................
14.11 BREAK GENERATION ........................................................................................................................
15.0 A/D Converter ...........................................................................................................................................
15.1 OPERATING MODES ...........................................................................................................................
15.1.1 A/D Control Register ........................................................................................................................
15.1.1.1 Channel Select ...........................................................................................................................
15.1.1.2 Multiplexor Output Select ...........................................................................................................
15.1.1.3 Mode Select ...............................................................................................................................
15.1.1.4 Prescaler Select .........................................................................................................................
15.1.1.5 Busy Bit ......................................................................................................................................
15.1.2 A/D Result Registers .......................................................................................................................
15.2 A/D OPERATION ...................................................................................................................................
15.2.1 Prescaler ..........................................................................................................................................
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