the shutdown signal is high the output will be disabled.
PROTECTION CIRCUITS
There are two conditions which will latch all the output tran-
sistors off. The first of these conditions is activation of the high
side current limit. Specifically, current in pin 7 (+V
S
) is moni-
tored. The DC trip level is about 35A and response time about
5us. As actual currents increase the response time decreases.
The external fault generally associated with this condition is
shorting one of the outputs to ground. However, a load fault
can also activate this high side current limit if the current rise
time is less than the response time of the filter discussed under
“Current Limit” The second of these conditions is activation of
.
any of the four output transistor over-temperature sensors at
about 165°C. Ambient temperature, air flow, amplifier mounting
problems and all the previously mentioned high current faults
contribute to junction temperature. When either of these pro-
tection circuits are activated, the root fault must be corrected
and power cycled to restore normal operation.
CURRENT LIMIT
The current limit function sets a peak limit on current flow in
pin 8 (Isense). This limits load current and also limits current
in the event of a short of either output to +Vs. This circuit can
trip anytime during the conduction period and will hold the
output transistors off for the remainder of that conduction period.
For proper operation the current limit sense resistor must
be connected as shown in the external connection diagram.
It is recommended that the resistor be a non-inductive type.
Load current flows in pin 8. No current flows in pin 10 (Shut-
down/filter) so no error will be introduced by the length of
the connection to pin 10. However, the voltage at pin 10 is
compared to GND (pin 4) and an error could be introduced if
the grounded end of R
LIMIT
is not directly tied to pin 4. Good
circuit board layout practice would be to connect R
LIMIT
directly
between pins 8 and 4.
Switching noise spikes will invariably be found at pin 8. The
amplitude and duration will be load dependent. The noise
spikes could trip the current limit threshold which is only 200
mV. R
FILTER
and C
FILTER
should be adjusted so as to reduce the
switching noise well below 200 mV to prevent false current
limiting. The sum of the DC level plus the noise peak will de-
termine the current limiting value. Suggested starting values
are C
FILTER
= .01µF, R
FILTER
= 5k.
The required value of R
LIMIT
may be calculated by:
R
LIMIT
= .2 V / I
LIMIT
where R
LIMIT
is the required resistor value, and I
LIMIT
is the
maximum desired current.
DEAD TIME
There is a dead time between the on and off of each out-
put. The dead time removes the possibility of a momentary
conduction path through the upper and lower transistors of
each half bridge output during the switching interval. During
the dead time all output transistors are off. Noise or flyback
may be observed at the outputs during this time due to the
high impedance of the outputs in the off state. This will vary
with the nature of the load.
REF OUT 5
.1µF
R1
R2
C2
TO TACH
SIGNAL
R4
–IN
+IN
R7
FIGURE 2.
C1
R3
R5
R6
1
2
3
E/A OUT
SHUTDOWN
The shutdown circuitry makes use of the internal current
limiting circuitry. The two functions may be externally combined
as shown below in Figure 1. R
LIMIT
will normally be a very low
value resistor and can be considered zero for this application.
R
SD
and R
FILTER
form a voltage divider for the shutdown signal.
After a suitable noise filter is designed for the current limit
adjust the value of R
SD
to give 317 mV of shutdown signal at
pin 10 when the shutdown signal is high. This means pin 10
will reach the 200 mV trip point in about one time constant
with low output current and
R
SD
less time as output current
SHDN/FILTER
SHUTDOWN
increases. The voltage at
SIGNAL
10
pin 10 is referenced to pin
4 (GND). C
FILTER
will filter
C
FILTER
R
FILTER
both the current limit noise
8
spikes and the shutdown
I
SENSE
signal. Shutdown and
R
LIMIT
current limit operate on
each cycle of the internal
FIGURE 1.
switching rate. As long as
4
ERROR AMPLIFIER
The internal error amplifier is an operational amplifier. For
highest loop accuracy it is best to configure the op amp as an
integrator (See Figure 2). Feedback can be adjusted with ap-
propriate poles and zeroes to properly compensate the velocity
loop for optimum stability.
The op amp is operated from a single supply voltage gener-
ated internally. The non-inverting input of the op amp does not
have a common mode range which includes ground. R2 and
R7 are used with the reference voltage provided at pin 5 to
bias the non-inverting input to +5 volts, which is approximately
half of the voltage supplied internally to the op amp. Similarly,
R1 and the parallel combination of R5 R6 are selected to bias
the inverting input also at +5 volts. Resistors R1 R2 must be
matched. Likewise the parallel combination of R5 R6 must
be matched with R7. The source impedances of the tach
and the signal source may affect the matching and should be
considered in the design.
SA01U
SA01 • SA01-6
NEED TECHNICAL HELP? CONTACT APEX SUPPORT!
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For inquiries via email, please contact apex.support@apexanalog.com.
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To find the one nearest to you, go to www.apexanalog.com
IMPORTANT NOTICE
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notice to any specifications or products mentioned herein to improve reliability. This document is the property of Apex Microtechnology and by furnishing this informa-
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property rights. Apex Microtechnology owns the copyrights associated with the information contained herein and gives consent for copies to be made of the informa-
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STOOD TO BE FULLY AT THE CUSTOMER OR THE CUSTOMER’S RISK.
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