NCP1083
Integrated High Power
PoE-PD Interface & DC-DC
Converter Controller with
9 V Auxiliary Supply Support
Introduction
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The NCP1083 is a member of ON Semiconductor’s high power
HIPO Power over Ethernet Powered Device (PoE−PD) product family
TSSOP−20 EP
DE SUFFIX
and represents a robust, flexible and highly integrated solution
CASE 948AB
targeting demanding medium and high power Ethernet applications. It
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combines in a single unit an enhanced PoE−PD interface supporting
the IEEE 802.3af and the 802.3at standard and a flexible and
configurable DC−DC converter controller.
The NCP1083’s exceptional capabilities enable applications to
smoothly transition from non−PoE to PoE enabled networks by also
supporting power from auxiliary sources such as AC power adapters
and battery supplies, eliminating the need for a second switching
power supply.
ON Semiconductor’s unique manufacturing process and design
enhancements allow the NCP1083 to deliver up to 25.5 W for the
IEEE 802.3at standard and up to 40 W for proprietary high power PoE
applications. The NCP1083 enables the IEEE 802.3at and implements
NCP1083 = Specific Device Code
a two event physical layer classification. Additional proprietary
XXXX = Date Code
Y
= Assembly Location
classification procedures support high power power sourcing
ZZ
= Traceability Code
equipment (PSE) on the market. The unique high power features
leverage the significant cost advantages of PoE− enabled systems to a
much broader spectrum of products in emerging markets such as
ORDERING INFORMATION
industrial ethernet devices, PTZ and Dome IP cameras, RFID readers,
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
MIMO WLAN access points, high−end VoIP phones, notebooks, etc.
The integrated current mode DC−DC controller facilitates
•
9 V Front, Rear and Direct Auxiliary Supply Connections
isolated and non−isolated fly−back, forward and buck
•
Supporting the IEEE 802.3af and the 802.3at Standard
converter topologies. It has all the features necessary for a
•
Supports IEEE 802.3at Two Event Layer 1
flexible, robust and highly efficient design including
Classification
programmable switching frequency, duty cycle up to 80
•
High Power Layer 1 Classification Indicator
percent, slope compensation, and soft start−up.
•
Extended Power Ranges up to 40 W
The NCP1083 is fabricated in a robust high voltage
process and integrates a rugged vertical N−channel DMOS
•
Programmable Classification Current
with a low loss current sense technique suitable for the most
•
Adjustable Under Voltage Lock Out
demanding environments and capable of withstanding harsh
•
Programmable Inrush Current Limit
environments such as hot swap and cable ESD events.
•
Programmable Operational Current Limit up to
The NCP1083 complements ON Semiconductor’s ASSP
1100 mA for Extended Power Ranges
portfolio in industrial devices and can be combined with
•
Over−temperature Protection
stepper motor drivers, CAN bus drivers and other high−
•
Industrial Temperature Range
−40°C
to 85°C with Full
voltage interfacing devices to offer complete solutions to the
Operation up to 150°C Junction Temperature
industrial and security market.
•
0.6
W
Hot−Swap Pass−switch with Low Loss Current
Features
Sense Technique
•
These are Pb−Free Devices
•
Vertical N−channel DMOS Pass−switch Offers the
Powered Device Interface
Robustness of Discrete MOSFETs with Integrated
Temperature Control
•
Flexible Auxiliary Power Supply Support
©
Semiconductor Components Industries, LLC, 2013
May, 2013
−
Rev. 3
1
Publication Order Number:
NCP1083/D
NCP1083
DC−DC Converter Controller
•
Current Mode Control
•
Supports Isolated and Non−isolated DC−DC Converter
•
•
•
•
Applications
Internal Voltage Regulators
Wide Duty Cycle Range with Internal Slope
Compensation Circuitry
Programmable Oscillator Frequency
Programmable Soft−start Time
PIN DIAGRAM
VPORTP
CLASS
UVLO
INRUSH
ILIM1
VPORTN1
RTN
VPORTN2
AUX
TEST
1
SS
FB
COMP
VDDL
VDDH
GATE
ARTN
nCLASS_AT
CS
OSC
Exposed
Pad
(Top View)
ORDERING INFORMATION
Part Number
NCP1083DEG
NCP1083DER2G
Temperature Range
−40°C
to 85°C
−40°C
to 85°C
Package
TSSOP−20 EP
(Pb−Free)
TSSOP−20 EP
(Pb−Free)
Shipping Configuration
†
74 units / Tube
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
VPORTP
DETECTION
INTERNAL
SUPPLY
&
BANDGAP
THERMAL
SHUT
DOWN
VDDH
VDDH
AUX
AUXILIARY
SUPPLY
DETECTION
VDDL
VDDL
VDDL
CLASS
CLASSIFICATION
VDDL
5
mA
SS
VDDL
UVLO
VPORT
MONITOR
5K
DC−DC
CONVERTER
CONTROL
1.2 V
FB
COMP
CS
OSC
HOT SWAP SWITCH
INRUSH
ILIM1
CONTROL & CURRENT
LIMIT BLOCKS
VDDL
20
mA
nCLASS_AT
ARTN
VPORTN1,2
RTN
VDDH
OSC
GATE
UVLO
INRUSH
ILIM1
Figure 1. NCP1083 Block Diagram
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NCP1083
SIMPLIFIED APPLICATION DIAGRAMS
VAUX(+)
RJ−45
DB1
Data
Pairs
Raux2
D2
DB2
Spare
Pairs
Raux3
R2
Z_line
D3
Cline
R1
Raux1
Rinrush
Rilim1
Rclass
VPORTP
CLASS
INRUSH
ILIM1
VDDH
Cpd
Cvddh
VDDL
Cvddl
LD1
Rd1
M1
Rslope
Rcs
Optocoupler R5
OC1
C2
R3
C1
Z1
R4
T1
D1
Voutput
Cload
NCP1083
nCLASS_AT
UVLO
GATE
AUX
CS
TEST
FB
VPORTN1
ARTN
VPORTN2
RTN
SS
OSC COMP
Rosc
Css
VAUX(−)
Figure 2. Isolated Fly−back Converter with Rear Auxiliary Supply
Figure 2 shows the integrated PoE−PD switch and DC−DC controller configured to work in a fully isolated application. The
output voltage regulation is accomplished with an external opto−coupler and a shunt regulator (Z1).
VAUX(+)
RJ−45
DB1
Data
Pairs
Raux2
D2
DB2
Raux3
Spare
Pairs
R2
Z_line
D3
Cline
R1
Raux1
Rinrush
Rilim1
Rclass
VPORTP
CLASS
INRUSH
ILIM1
VDDH
Cpd
Cvddh
VDDL
Cvddl
LD1
Rd1
M1
Rslope
Rcs
R4
R3
T1
D1
Voutput
Cload
NCP1083
nCLASS_AT
UVLO
GATE
AUX
CS
TEST
FB
VPORTN1
ARTN
VPORTN2
RTN
SS
OSC COMP
Rosc
Css
Rcomp
C1comp
C2comp
VAUX(−)
Figure 3. Non−Isolated Fly−back Converter with Rear Auxiliary Supply
Figure 3 shows the integrated PoE−PD and DC−DC controller configured in a non−isolated fly−back configuration. A
compensation network is inserted between the FB and the COMP pin for overall stability of the feedback loop.
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3
NCP1083
SIMPLIFIED APPLICATION DIAGRAMS
VAUX(+)
RJ−45
DB1
Data
Pairs
Raux2
D3
DB2
Raux3
Spare
Pairs
R2
Z_line
D4
Cline
R1
Raux1
Rinrush
Rilim1
Rclass
VPORTP
CLASS
INRUSH
ILIM1
R5
Cvddh
Cpd
LD1
Cvddl
Rd1
M1
Rslope
Rcs
R4
D2
VDDH
T1
D1
Voutput
VDDL
R3
Cload
NCP1083
nCLASS_AT
UVLO
GATE
AUX
CS
TEST
FB
VPORTN1
ARTN
VPORTN2
RTN
SS
OSC COMP
Rosc
Css
Rcomp
C1comp
C2comp
VAUX(−)
Figure 4. Non−Isolated Fly−back with Extra Winding and Rear Auxiliary Supply
Figure 4 shows the same non−isolated fly−back configuration as Figure 3, but adds a 12 V auxiliary bias winding on the
transformer to provide power to the NCP1083 DC−DC controller via its VDDH pin. This topology shuts off the current flowing
from VPORTP to VDDH and therefore reduces the internal power dissipation of the PD, resulting in higher overall power
efficiency.
VAUX(+)
RJ−45
DB1
Data
Pairs
Raux2
D4
DB2
Raux3
Spare
Pairs
R2
Z_line
D5
Cline
R1
Raux1
Rinrush
Rilim1
Rclass
VPORTP
CLASS
INRUSH
ILIM1
Cpd
VDDH
VDDL
Cvddl
Cvddh
LD1
Rd1
M1
Rslope
Rcs
R3
R4
D2
Cload
D3 T1
D1
L1
Voutput
NCP1083
nCLASS_AT
UVLO
GATE
AUX
CS
TEST
FB
VPORTN1
ARTN
VPORTN2
RTN
SS
OSC COMP
Rosc
Css
Rcomp
C1comp
C2comp
VAUX(−)
Figure 5. Non−Isolated Forward Converter with Rear Auxiliary Supply
Figure 5 shows the NCP1083 used in a non−isolated forward topology.
High Power Considerations
The NCP1083 is designed to implement various
configurations of high−power PoE systems including those
based on the IEEE 802.3at standard. High power operation
can be enabled by a Dual Event Layer 1 classification or a
Single Event Layer 1 classification combined with a Layer 2
high power classification. The NCP1083 also supports
proprietary designs capable of delivering 25 W to 40 W to
the load in two−pair configurations. A separate application
note describes these implementations (AND8332).
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4
NCP1083
Table 1. PIN DESCRIPTIONS
Name
VPORTP
VPORTN1
VPORTN2
RTN
ARTN
VDDH
Pin No.
1
6,8
7
14
16
Type
Supply
Ground
Ground
Ground
Supply
Description
Positive input power. Voltage with respect to VPORTN
1,2
.
Negative input power. Connected to the source of the internal pass−switch.
DC−DC controller power return. Connected to the drain of the internal pass−switch. It must
be connected to ARTN. This pin is also the drain of the internal pass−switch.
DC−DC controller ground pin. Must be connected to RTN as a single point ground connection
for improved noise immunity.
Output of the 9 V LDO internal regulator. Voltage with respect to ARTN. Supplies the internal
gate driver. VDDH must be bypassed to ARTN with a 1
mF
or 2.2
mF
ceramic capacitor with
low ESR.
Output of the 3.3 V LDO internal regulator. Voltage with respect to ARTN. This pin can be
used to bias an external low−power LED (1 mA max.) connected to nCLASS_AT, and can
also be used to add extra biasing current in the external opto−coupler. VDDL must be by-
passed to ARTN with a 330 nF or 470 nF ceramic capacitor with low ESR.
Classification current programming pin. Connect a resistor between CLASS and VPORTN
1,2
.
Inrush current limit programming pin. Connect a resistor between INRUSH and VPORTN
1,2
.
Operational current limit programming pin. Connect a resistor between ILIM1 and
VPORTN
1,2
.
DC−DC controller under−voltage lockout input. Voltage with respect to VPORTN
1,2
. Connect
a resistor−divider from VPORTP to UVLO to VPORTN
1,2
to set an external UVLO threshold.
DC−DC controller gate driver output pin.
Internal oscillator frequency programming pin. Connect a resistor between OSC and ARTN.
Active−low, open−drain Layer 1 dual−finger classification indicator.
Output of the internal error amplifier of the DC−DC controller. COMP is pulled−up internally to
VDDL with a 5 kW resistor. In isolated applications, COMP is connected to the collector of the
opto−coupler. Voltage with respect to ARTN.
DC−DC controller inverting input of the internal error amplifier. In isolated applications, the pin
should be strapped to ARTN to disable the internal error amplifier.
Current−sense input for the DC−DC controller. Voltage with respect to ARTN.
Soft−start input for the DC−DC controller. A capacitor between SS and ARTN determines the
soft−start timing.
When the pin is pulled up, the IEEE detection mode is disabled and the device can be sup-
plied by an auxiliary supply. Voltage with respect to VPORTN
1,2
. Connect the pin to the auxili-
ary supply through a resistor divider.
Digital test pin must always be connected to VPORTN
1,2
.
Exposed pad. Connected to VPORTN
1,2
ground.
VDDL
17
Supply
CLASS
INRUSH
ILIM1
UVLO
GATE
OSC
nCLASS_AT
COMP
2
4
5
3
15
11
13
18
Input
Input
Input
Input
Output
Input
Output,
Open Drain
I/O
FB
CS
SS
AUX
19
12
20
9
Input
Input
Input
Input
TEST
EP
10
Input
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