NCP1081
Integrated High Power
PoE-PD Interface & DC-DC
Converter Controller
Introduction
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The NCP1081 is a member of ON Semiconductor’s high power
HIPO Power over Ethernet Powered Device (PoE−PD) product family
and represents a robust, flexible and highly integrated solution
targeting demanding medium and high power Ethernet applications. It
combines in a single unit an enhanced PoE−PD interface supporting
1
the IEEE802.3af and the 802.3at standard and a flexible and
TSSOP−20 EP
configurable DC−DC converter controller.
DE SUFFIX
The NCP1081’s exceptional capabilities offer new opportunities for
CASE 948AB
the design of products powered directly over Ethernet lines,
eliminating the need for local power adaptors or power supplies and
drastically reducing the overall installation and maintenance cost.
ON Semiconductor’s unique manufacturing process and design
enhancements allow the NCP1081 to deliver up to 25.5 W for the
IEEE802.3at standard and up to 40 W for proprietary high power PoE
applications. The NCP1081 enables the IEEE802.3at and implements
a two event physical layer classification. Additional proprietary
classification procedures support high power power sourcing
equipment (PSE) on the market. The unique high power features
leverage the significant cost advantages of PoE− enabled systems to a
much broader spectrum of products in emerging markets such as
NCP1081 = Specific Device Code
industrial ethernet devices, PTZ and Dome IP cameras, RFID readers,
XXXX = Date Code
MIMO WLAN access points, high end VoIP phones, notebooks, etc.
Y
= Assembly Location
The integrated current mode DC−DC controller facilitates isolated
ZZ
= Traceability Code
and non−isolated fly−back, forward and buck converter topologies. It
has all the features necessary for a flexible, robust and highly efficient
design including programmable switching frequency, duty cycle up to
ORDERING INFORMATION
See detailed ordering and shipping information in the package
80 percent, slope compensation, and soft start−up.
dimensions section on page 2 of this data sheet.
The NCP1081 is fabricated in a robust high voltage
process and integrates a rugged vertical N−channel DMOS
with a low loss current sense technique suitable for the most
•
Extended Power Ranges up to 40 W
demanding environments and capable of withstanding harsh
•
Programmable Classification Current
environments such as hot swap and cable ESD events.
•
Adjustable Under Voltage Lock Out
The NCP1081 complements ON Semiconductor’s ASSP
•
Programmable Inrush Current Limit
portfolio in industrial devices and can be combined with
•
Programmable Operational Current Limit up to
stepper motor drivers, CAN bus drivers and other high−
1100 mA for Extended Power Ranges
voltage interfacing devices to offer complete solutions to the
industrial and security market.
•
Over−temperature Protection
•
Industrial Temperature Range
−40°C
to 85°C with Full
Features
Operation up to 150°C Junction Temperature
•
These are Pb−Free Devices
•
0.6
W
Hot−swap Pass−switch with Low Loss Current
Powered Device Interface
Sense Technique
•
Supporting the IEEE802.3af and the 802.3at Standard
•
Vertical N−channel DMOS Pass−switch offers the
•
Supports IEEE802.3at Two Event Layer 1
Robustness of Discrete MOSFETs with Integrated
Classification
Temperature Control
•
High Power Layer 1 Classification Indicator
©
Semiconductor Components Industries, LLC, 2013
May, 2013
−
Rev. 7
1
Publication Order Number:
NCP1081/D
NCP1081
DC−DC Converter Controller
•
Current Mode Control
•
Supports Isolated and Non−isolated DC−DC Converter
•
•
•
•
Applications
Internal Voltage Regulators
Wide Duty Cycle Range with Internal Slope
Compensation Circuitry
Programmable Oscillator Frequency
Programmable Soft−start Time
PIN DIAGRAM
VPORTP
CLASS
UVLO
INRUSH
ILIM1
VPORTN1
RTN
VPORTN2
TEST1
TEST2
1
SS
FB
COMP
VDDL
VDDH
GATE
ARTN
nCLASS_AT
CS
OSC
Exposed
Pad
(Top View)
ORDERING INFORMATION
Part Number
NCP1081DEG
NCP1081DER2G
Package
TSSOP−20 EP
(Pb−Free)
TSSOP−20 EP
(Pb−Free)
Shipping Configuration
†
74 units / Tube
2500 / Tape & Reel
Temperature Range
−40°C
to 85°C
−40°C
to 85°C
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
VPORTP
DETECTION
INTERNAL
SUPPLY
&
BANDGAP
THERMAL
SHUT
DOWN
VDDH
VDDH
VDDL
VDDL
CLASS
CLASSIFICATION
VDDL
VDDL
5
mA
SS
UVLO
UVLO
VPORT
MONITOR
DC−DC
CONVERTER
CONTROL
VDDL
5 K 1.2 V
FB
COMP
CS
INRUSH
ILIM1
INRUSH
ILIM1
OSC
HOT SWAP SWITCH
CONTROL & CURRENT
LIMIT BLOCKS
VDDL
20
mA
VDDH
OSC
GATE
nCLASS_AT
ARTN
VPORTN1,2
RTN
Figure 1. NCP1081 Block Diagram
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NCP1081
SIMPLIFIED APPLICATION DIAGRAMS
VPORTP
CLASS
VDDH
Cvddh
Cpd
T1
D1
Voutput
RJ−45
Rclass
Z_line
Cline
Data
Pairs
Rinrush
DB1
INRUSH
VDDL
NCP1081
nCLASS_AT
GATE
CS
FB
ARTN
RTN
COMP
Rilim1
R1
Cvddl
LD1
Rd1
M1
R5
OC1
Rcs
C2
C1
R3
Optocoupler
Cload
ILIM1
UVLO
R2
TEST2
TEST1
VPORTN1
OSC
Rslope
Spare
Pairs
DB2
VPORTN2
Css
Figure 2. Isolated Fly−back Converter
Figure 2 shows the integrated PoE−PD switch and DC−DC controller configured to work in a fully isolated application. The
output voltage regulation is accomplished with an external opto−coupler and a shunt regulator (Z1).
RJ−45
Rclass
VPORTP
CLASS
VDDH
SS
Rosc
Z1
R4
Cpd
T1
Cvddh
Voutput
Z_line
Cline
Data
Pairs
Rinrush
DB1
INRUSH
VDDL
NCP1081
nCLASS_AT
Cvddl
LD1
R3
M1
Cload
Rilim1
R1
ILIM1
Rd1
GATE
CS
FB
ARTN
RTN
COMP
UVLO
R2
TEST2
TEST1
VPORTN1
VPORTN2
OSC
SS
Rslope
Rcs
R4
Spare
Pairs
DB2
Css Rosc
C1comp Rcomp
C2comp
Figure 3. Non−Isolated Fly−back Converter
Figure 3 shows the integrated PoE−PD and DC−DC controller configured in a non−isolated fly−back configuration. A
compensation network is inserted between the FB and the COMP pin for overall stability of the feedback loop.
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3
NCP1081
SIMPLIFIED APPLICATION DIAGRAMS
D2
RJ−45
VPORTP
CLASS
VDDH
R5
Cpd
Cvddh
INRUSH
VDDL
NCP1081
nCLASS_AT
UVLO
R2
TEST2
TEST1
COMP
VPORTN1
VPORTN2
OSC
SS
GATE
CS
FB
ARTN
RTN
Rcs
Rslope
R4
Cvddl
LD1
Cload
Rd1
M1
R3
T1
Rclass
D1
Voutput
Rinrush
Cline
DB1
Z_line
Data
Pairs
Rilim1
R1
ILIM1
Spare
Pairs
DB2
Css Rosc
C1comp Rcomp
C2comp
Figure 4. Non−Isolated Fly−back with Extra Winding
Figure 4 shows the same non−isolated fly−back configuration as Figure 3, but adds a 12 V auxiliary bias winding on the
transformer to provide power to the NCP1081 DC−DC controller via its VDDH pin. This topology shuts off the current flowing
from VPORTP to VDDH and therefore reduces the internal power dissipation of the PD, resulting in higher overall power
efficiency.
D3
Cpd
RJ−45
Rclass
VPORTP
CLASS
VDDH
D1
Cvddh
T1
L1
Voutput
D2
Z_line
Cline
Data
Pairs
Rinrush
DB1
INRUSH
VDDL
NCP1081
nCLASS_AT
GATE
CS
FB
ARTN
RTN
COMP
OSC
SS
Cvddl
LD1
Rd1
M1
R3
Cload
Rilim1
R1
ILIM1
UVLO
R2
TEST2
TEST1
VPORTN1
VPORTN2
Rslope
R4
Rcs
Spare
Pairs
DB2
Css Rosc
C1comp Rcomp
C2comp
Figure 5. Non−Isolated Forward Converter
Figure 5 shows the NCP1081 used in a non−isolated forward topology.
High Power Considerations
The NCP1081 is designed to implement various
configurations of high−power PoE systems including those
based on the IEEE802.3at standard. High power operation
can be enabled by a Dual Event Layer 1 classification or a
Single Event Layer 1 classification combined with a Layer 2
high power classification. The NCP1081 also supports
proprietary designs capable of delivering 25 W to 40 W to
the load in two−pair configurations. A separate application
note describes these implementations (AND8332).
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4
NCP1081
Table 1. PIN DESCRIPTIONS
Name
VPORTP
VPORTN1
VPORTN2
RTN
ARTN
VDDH
Pin No.
1
6,8
7
14
16
Type
Supply
Ground
Ground
Ground
Supply
Description
Positive input power. Voltage with respect to VPORTN
1,2
.
Negative input power. Connected to the source of the internal pass−switch.
DC−DC controller power return. Connected to the drain of the internal pass−switch. It must
be connected to ARTN. This pin is also the drain of the internal pass−switch.
DC−DC controller ground pin. Must be connected to RTN as a single point ground connection
for improved noise immunity.
Output of the 9 V LDO internal regulator. Voltage with respect to ARTN. Supplies the internal
gate driver. VDDH must be bypassed to ARTN with a 1
mF
or 2.2
mF
ceramic capacitor with
low ESR.
Output of the 3.3 V LDO internal regulator. Voltage with respect to ARTN. This pin can be
used to bias an external low−power LED (1 mA max.) connected to nCLASS_AT, and can
also be used to add extra biasing current in the external opto−coupler. VDDL must be by-
passed to ARTN with a 330 nF or 470 nF ceramic capacitor with low ESR.
Classification current programming pin. Connect a resistor between CLASS and VPORTN
1,2
.
Inrush current limit programming pin. Connect a resistor between INRUSH and VPORTN
1,2
.
Operational current limit programming pin. Connect a resistor between ILIM1 and
VPORTN
1,2
.
DC−DC controller under−voltage lockout input. Voltage with respect to VPORTN
1,2
. Connect
a resistor−divider from VPORTP to UVLO to VPORTN
1,2
to set an external UVLO threshold.
DC−DC controller gate driver output pin.
Internal oscillator frequency programming pin. Connect a resistor between OSC and ARTN.
Active−low, open−drain Layer 1 dual−finger classification indicator.
Output of the internal error amplifier of the DC−DC controller. COMP is pulled−up internally to
VDDL with a 5 kW resistor. In isolated applications, COMP is connected to the collector of the
opto−coupler. Voltage with respect to ARTN.
DC−DC controller inverting input of the internal error amplifier. In isolated applications, the pin
should be strapped to ARTN to disable the internal error amplifier.
Current−sense input for the DC−DC controller. Voltage with respect to ARTN.
Soft−start input for the DC−DC controller. A capacitor between SS and ARTN determines the
soft−start timing.
Digital test pin must always be connected to VPORTN
1,2
.
Digital test pin must always be connected to VPORTN
1,2
.
Exposed pad. Connected to VPORTN
1,2
ground.
VDDL
17
Supply
CLASS
INRUSH
ILIM1
UVLO
GATE
OSC
nCLASS_AT
COMP
2
4
5
3
15
11
13
18
Input
Input
Input
Input
Output
Input
Output,
Open Drain
I/O
FB
CS
SS
TEST1
TEST2
EP
19
12
20
9
10
Input
Input
Input
Input
Input
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5
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