HD74LVC240A
Octal Buffers / Line Drivers with 3-state Outputs
REJ03D0351–0400Z
(Previous ADE-205-109B (Z))
Rev.4.00
Jul. 26, 2004
Description
The HD74LVC240A has eight inverter drivers with three state outputs in a 20 pin package. This device is an inverting
buffer and has two active low enables (1G and 2G). Each enable independently controls four buffers. Low voltage and
high-speed operation is suitable at the battery drive product (note type personal computer) and low power consumption
extends the life of a battery for long time operation.
Features
•
•
•
•
•
•
•
V
CC
= 2.0 V to 5.5 V
All inputs V
IH
(Max.) = 5.5 V (@V
CC
= 0 V to 5.5 V)
All outputs V
OUT
(Max.) = 5.5 V (@V
CC
= 0 V or output off state)
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25°C)
Typical V
OH
undershoot > 2.0 V (@V
CC
= 3.3 V, Ta = 25°C)
High output current ±24 mA (@V
CC
= 3.0 V to 5.5 V)
Ordering Information
Package Type
SOP–20 pin (JEITA)
TSSOP–20 pin
Package Code
FP–20DAV
TTP–20DAV
Package
Abbreviation
FP
T
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
ELL (2,000 pcs/reel)
Part Name
HD74LVC240AFPEL
HD74LVC240ATELL
Note: Please consult the sales office for the above package availability.
Function Table
Inputs
G
H
L
L
H:
L:
X:
Z:
High level
Low level
Immaterial
High impedance
A
X
H
L
Output
Y
Z
L
H
Rev.4.00 Jul. 26, 2004 page 1 of 6
HD74LVC240A
Pin Arrangement
1G 1
1A1 2
2Y4 3
1A2 4
2Y3 5
1A3 6
2Y2 7
1A4 8
2Y1 9
GND 10
20 V
CC
19 2G
18 1Y1
17 2A4
16 1Y2
15 2A3
14 1Y3
13 2A2
12 1Y4
11 2A1
(Top view)
Absolute Maximum Ratings
Item
Supply voltage
Input diode current
Input voltage
Output diode current
Output voltage
Output current
V
CC
, GND current / pin
Storage temperature
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
or I
GND
Tstg
Ratings
–0.5 to 6.0
–50
–0.5 to 6.0
–50
50
–0.5 to V
CC
+0.5
–0.5 to 6.0
±50
100
–65 to +150
Unit
V
mA
V
mA
V
mA
mA
°C
Conditions
V
I
= –0.5 V
V
O
= –0.5 V
V
O
= V
CC
+0.5 V
Output "H" or "L"
Output "Z" or V
CC
:OFF
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
Rev.4.00 Jul. 26, 2004 page 2 of 6
HD74LVC240A
Recommended Operating Conditions
Item
Supply voltage
Input / output voltage
Symbol
V
CC
V
I
V
O
Ta
I
OH
I
OL
Input rise / fall time
*1
t
r
, t
f
Ratings
1.5 to 5.5
2.0 to 5.5
0 to 5.5
0 to V
CC
0 to 5.5
–40 to 85
–12
–24
*2
12
24
*2
10
Unit
V
V
V
°C
mA
mA
ns/V
Conditions
Data hold
At operation
G,
A
Output "H" or "L"
Output "Z" or V
CC
:OFF
V
CC
= 2.7 V
V
CC
= 3.0 V to 5.5 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 5.5 V
Operating temperature
Output current
Notes: 1. This item guarantees maximum limit when one input switches.
Waveform: Refer to test circuit of switching characteristics.
2. Duty cycle
≤
50%
Electrical Characteristics
Ta = –40 to 85°C
Item
Input voltage
Symbol
V
IH
V
IL
Output voltage
V
OH
V
CC
(V)
2.7 to 3.6
4.5 to 5.5
2.7 to 3.6
4.5 to 5.5
2.7 to 5.5
2.7
3.0
3.0
4.5
2.7 to 5.5
2.7
3.0
4.5
0 to 5.5
2.7 to 5.5
0
2.7 to 3.6
2.7 to 5.5
3.0 to 3.6
Min
2.0
V
CC
×0.7
—
—
V
CC
–0.2
2.2
2.4
2.2
3.8
—
—
—
—
—
—
—
—
—
—
Max
—
—
0.8
V
CC
×0.3
—
—
—
—
—
0.2
0.4
0.55
0.55
±5.0
±5.0
20
±10
10
500
Unit
V
V
V
I
OH
= –100 µA
I
OH
= –12 mA
I
OH
= –24 mA
V
I
OL
= 100 µA
I
OL
= 12 mA
I
OL
= 24 mA
V
IN
= 5.5 V
CC
or GND
V
IN
= V
CC
, GND
V
OUT
= 5.5 V or GND
V
IN
/ V
OUT
= 5.5 V
V
IN
/ V
OUT
= 3.6 to 5.5 V
V
IN
= V
CC
or GND
V
IN
= one input at (V
CC
–0.6)V,
other inputs at V
CC
or GND
Test Conditions
V
OL
Input current
Off state output current
Output leak current
Quiescent supply current
I
IN
I
OZ
I
OFF
I
CC
∆I
CC
µA
µA
µA
µA
µA
Rev.4.00 Jul. 26, 2004 page 3 of 6
HD74LVC240A
Switching Characteristics
Ta = –40 to 85°C
Item
Propagation delay time
Symbol
t
PLH
t
PHL
t
ZH
t
ZL
t
HZ
t
LZ
V
CC
(V)
2.7
3.3±0.3
5.0±0.5
2.7
3.3±0.3
5.0±0.5
2.7
3.3±0.3
5.0±0.5
2.7
3.3±0.3
5.0±0.5
2.7
2.7
Min
—
1.5
—
—
1.5
—
—
1.5
—
—
—
—
—
—
Typ
—
—
—
—
—
—
—
—
—
—
—
—
3.0
15.0
Max
7.5
6.5
5.0
9.0
8.0
6.5
8.0
7.0
6.0
—
1.0
1.0
—
—
Unit
ns
From
(Input)
A
To
(Output)
Y
Output enable time
ns
G
Y
Output disable time
ns
G
Y
Between output pins skew t
OSLH
*1
t
OSHL
Input capacitance
Output capacitance
Note:
C
IN
C
O
ns
pF
pF
1. This parameter is characterized but not tested.
tos
LH
= | t
PLHm
- t
PLHn
|, tos
HL
= | t
PHLm
- t
PHLn
|
Test Circuit
V
CC
V
CC
1G, 2G
Output
500
Ω
S1
C
L
=
50 pF
450
Ω
50
Ω
Scope
OPEN
See under table
GND
See Function Table
Input
1Y1 to 2Y4
*1
Pulse generator
Z
out
= 50
Ω
1A1 to 2A4
Symbol
t
PLH
/ t
PHL
t
ZH
/ t
HZ
t
ZL
/ t
LZ
S1
Vcc=2.7V,
3.3±0.3V
Vcc=5.0±0.5V
OPEN
GND
6V
OPEN
GND
2×Vcc
Note:
1. C
L
includes probe and jig capacitance.
Rev.4.00 Jul. 26, 2004 page 4 of 6
HD74LVC240A
Waveforms – 1
t
f
Input A
90 %
V
ref
t
r
90 %
10 %
t
PLH
Output Y
V
ref
10 %
t
PHL
V
OH
V
ref
V
OL
V
IH
GND
Notes:
1. t
r
= 2.5 ns, t
f
= 2.5 ns
2. Input waveform : PRR = 10 MHz, duty cycle 50%
Waveforms – 2
t
f
Input G
90 %
V
ref
10 %
t
ZL
Waveform - A
t
ZH
Waveform - B
V
ref
V
ref
t
HZ
V
OH
– 0.3 V
t
r
90 %
V
ref
10 %
t
LZ
V
IH
GND
≈V
OH1
V
OL
+ 0.3 V
V
OL
V
OH
≈V
OL1
TEST
V
IH
V
ref
V
OH1
V
OL1
Vcc=2.7V,
3.3±0.3V
Vcc=5.0±0.5V
2.7 V
1.5 V
3V
GND
Vcc
50%Vcc
Vcc
GND
Notes:
1. t
r
= 2.5 ns, t
f
= 2.5 ns
2. Input waveform : PRR = 10 MHz, duty cycle 50%
3. Waveform – A shows input conditions such that the output is "L" level when enable by the
output control.
4. Waveform – B shows input conditions such that the output is "H" level when enable by the
output control.
Rev.4.00 Jul. 26, 2004 page 5 of 6
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