LPC47N227
100 Pin Super I/O with LPC Interface for
Notebook Applications
FEATURES
3.3 Volt Operation (5V Tolerant)
PC99 and ACPI 1.0b Compliant
Programmable Wakeup Event Interface
(nIO_PME Pin)
SMI Support (nIO_SMI Pin)
GPIOs (29)
Two IRQ Input Pins
XNOR Chain
Intelligent Auto Power Management
2.88MB Super I/O Floppy Disk Controller
-
Licensed CMOS 765B Floppy Disk
Controller
-
Software and Register Compatible with
SMSC's Proprietary 82077AA
Compatible Core
Supports One Floppy Drive Directly
-
-
Configurable Open Drain/Push-Pull
Output Drivers
-
Supports Vertical Recording Format
-
16-Byte Data FIFO
100% IBM Compatibility
-
-
Detects All Overrun and Underrun
Conditions
-
Sophisticated Power Control Circuitry
(PCC) Including Multiple Powerdown
Modes for Reduced Power
Consumption
-
DMA Enable Logic
-
Data Rate and Drive Control Registers
-
Swap Drives A and B
-
Non-Burst Mode DMA Option
-
48 Base I/O Address, 15 IRQ and 3
DMA Options
-
Forceable Write Protect and Disk
Change Controls
Floppy Disk Available on Parallel Port Pins
(ACPI Compliant)
Enhanced Digital Data Separator
-
2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps,
250 Kbps Data Rates
-
Programmable Precompensation
Modes
Serial Ports
-
Two Full Function Serial Ports
-
High Speed NS16C550 Compatible
UARTs with Send/Receive 16-Byte
FIFOs
-
Supports 230k and 460k Baud
-
Programmable Baud Rate Generator
-
Modem Control Circuitry
Infrared Communications Controller
IrDA v1.2 (4Mbps), HPSIR, ASKIR,
-
Consumer IR Support
-
2 IR Ports
-
96 Base I/O Address, 15 IRQ Options
and 3 DMA Options
Multi-Mode Parallel Port with ChiProtect
-
Standard Mode IBM PC/XT, PC/AT,
and PS/2 Compatible Bidirectional
Parallel Port
-
Enhanced Parallel Port (EPP)
Compatible - EPP 1.7 and EPP 1.9
(IEEE 1284 Compliant)
-
IEEE 1284 Compliant Enhanced
Capabilities Port (ECP)
-
ChiProtect Circuitry for Protection
Against Damage Due to Printer Power-
On
-
192 Base I/O Address, 15 IRQ and 3
DMA Options
ORDERING INFORMATION
Order Numbers:
LPC47N227TQFP for 100 Pin TQFP Package
LPC47N227-MN for 100 Pin STQFP Package
LPC Bus Host Interface
-
Multiplexed Command, Address and
Data Bus
-
8-Bit I/O Transfers
-
8-Bit DMA Transfers
-
16-Bit Address Qualification
Serial IRQ Interface Compatible with
Serialized IRQ Support for PCI
Systems
-
PCI nCLKRUN Support
-
Power Management Event (nIO_PME)
Interface Pin
100 Pin TQFP Package and
STQFP
Package
-
GENERAL DESCRIPTION
The SMSC LPC47N227 is a 3.3V PC 99 and
ACPI 1.0b compliant Super I/O Controller. The
LPC47N227 implements the LPC interface, a pin
reduced ISA interface which provides the same
or better performance as the ISA/X-bus with a
substantial savings in pins used. The part also
includes 29 GPIO pins.
The LPC47N227 incorporates SMSC’s true
CMOS 765B floppy disk controller, advanced
digital data separator, 16-byte data FIFO, two
16C550 compatible UARTs, one Multi-Mode
parallel port with ChiProtect circuitry plus EPP
and ECP support and one floppy direct drive
support. The LPC47N227 does not require any
external filter components, is easy to use and
offers lower system cost and reduced board
area. The LPC47N227 is software and register
compatible with SMSC’s proprietary 82077AA
core.
The true CMOS 765B core provides 100%
compatibility with IBM PC/XT and PC/AT
architectures and provides data overflow and
underflow protection.
The SMSC advanced
digital data separator incorporates SMSC’s
patented data separator technology allowing for
ease of testing and use. The LPC47N227
supports both 1Mbps and 2Mbps data rates and
vertical recording operation at 1Mbps Data Rate.
The LPC47N227 also features a full 16-bit
internally decoded address bus, a Serial IRQ
interface with PCI nCLKRUN support, relocatable
configuration ports and three DMA channel
options.
Both on-chip UARTs are compatible with the
NS16C550.
One UART includes additional
support for a Serial Infrared Interface that
complies with IrDA v1.2 (Fast IR), HPSIR, and
ASKIR formats (used by Sharp and other PDAs),
as well as Consumer IR.
The parallel port is compatible with IBM PC/AT
architectures, as well as IEEE 1284 EPP and
ECP.
The parallel port ChiProtect circuitry
prevents damage caused by an attached
powered printer when the LPC47N227 is not
powered.
The LPC47N227 incorporates sophisticated
power control circuitry (PCC). The PCC supports
multiple low power down modes.
The
LPC47N227 also features Software Configurable
Logic (SCL) for ease of use.
SCL allows
programmable system configuration of key
functions such as the FDC, parallel port, and
UARTs.
The LPC47N227 supports the ISA Plug-and-Play
Standard (Version 1.0a) and provides the
recommended functionaity to support Windows
‘95/’98 and PC99. The I/O Address, DMA
Channel and Hardware IRQ of each device in the
LPC47N227 may be reprogrammed through the
internal configuration registers. There are 192
I/O address location options, a Serialized IRQ
interface, and three DMA channels.
2
TABLE OF CONTENTS
FEATURES.............................................................................................................................................. 1
GENERAL DESCRIPTION ...................................................................................................................... 2
PIN CONFIGURATION............................................................................................................................ 4
DESCRIPTION OF PIN FUNCTIONS ..................................................................................................... 5
Buffer Type Description.......................................................................................................................12
BLOCK DIAGRAM .................................................................................................................................13
3.3 VOLT OPERATION / 5 VOLT TOLERANCE ...................................................................................14
Power Functionality..............................................................................................................................14
VCC Power..........................................................................................................................................14
VTR Support .......................................................................................................................................14
Internal PWRGOOD ............................................................................................................................14
Trickle Power Functionality..................................................................................................................14
Maximum Current Values ....................................................................................................................15
Power Management Events (PME/SCI) ..............................................................................................15
FUNCTIONAL DESCRIPTION ...............................................................................................................16
FLOPPY DISK CONTROLLER ..............................................................................................................21
SERIAL PORT (UART)...........................................................................................................................68
INFRARED INTERFACE ........................................................................................................................85
PARALLEL PORT ..................................................................................................................................89
POWER MANAGEMENT .....................................................................................................................111
SERIAL IRQ .........................................................................................................................................115
PCI CLKRUN SUPPORT .....................................................................................................................119
GENERAL PURPOSE I/O ....................................................................................................................122
SYSTEM MANAGEMENT INTERRUPT (SMI) .....................................................................................128
PME SUPPORT....................................................................................................................................129
RUNTIME REGISTERS........................................................................................................................130
CONFIGURATION................................................................................................................................137
OPERATIONAL DESCRIPTION ..........................................................................................................172
Maximum Guaranteed Ratings..........................................................................................................172
DC Electrical Characteristics .............................................................................................................172
TIMING DIAGRAMS .............................................................................................................................176
PACKAGE OUTLINE ...........................................................................................................................197
3
PIN CONFIGURATION
Note:
Pinouts are the same for both the TQFP and STQFP Packages.
DRVDEN0
DRVDEN1
nMTR0
nDSKCHG
nDS0
GP24
VSS
nDIR
nSTEP
nWDATA
nWGATE
nHDSEL
nINDEX
nTRK0
nWRTPRT
nRDATA
nIO_PME
VTR
CLOCKI
LAD0
LAD1
LAD2
LAD3
nLFRAME
nLDRQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
nDTR2
nCTS2
nRTS2
nDSR2
TXD2
RXD2
nDCD2
VCC
nRI2
nDCD1
nRI1
nDTR1
nCTS1
nRTS1
nDSR1
TXD1
RXD1
nSTROBE
nALF
nERROR
nACK
BUSY
PE
SLCT
VSS
LPC47N227
100 Pin TQFP
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
nSLCTIN
nINIT
VCC
GP23/FDC_PP
IRMODE/IRRX3
IRTX2
IRRX2
VSS
GP22
GP21
GP20
GP17
GP16
GP15
VCC
GP14/IRQIN2
GP13/IRQIN1
nPCI_RESET
nLPCPD
nCLKRUN
PCI_CLK
SER_IRQ
VSS
GP30
GP31
GP32
GP33
GP34
GP35
GP36
GP37
GP40
GP41
GP42
GP43
GP44
GP45
GP46
GP47
GP10
GP11/SYSOPT
GP12/nIO_SMI
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
4
DESCRIPTION OF PIN FUNCTIONS
TQFP/STQFP
PIN #
23:20
24
25
26
27
28
29
30
17
BUFFER
TYPE PER
1
SYMBOL
FUNCTION
LPC INTERFACE
LAD[3:0]
PCI_IO
NAME
LPC Address/
Data bus 3-0
LPC Frame
LPC
DMA/Bus Master
Request
PCI RESET
LPC Power Down
(Note 2)
PCI Clock
Controller
PCI Clock
Serial IRQ
Power Mgt. Event
(Note 7)
DESCRIPTION
1
2
3
4
Drive Density 0
Drive Density 1
Motor On 0
Disk Change
Active high LPC signals used for
multiplexed command, address and data
bus.
nLFRAME
PCI_I
Active low signal indicates start of new
cycle and termination of broken cycle.
nLDRQ
PCI_O
Active low signal used for encoded
DMA/Bus Master request for the LPC
interface.
nPCI_RESE
PCI_I
Active low signal used as LPC Interface
T
Reset.
nLPCPD
PCI_I
Active low Power Down signal indicates
that the LPC47N227 should prepare for
power to be shut on the LPC interface.
nCLKRUN
PCI_OD
This signal is used to indicate the PCI
clock status and to request that a stopped
clock be started.
PCI_CLK
PCI_CLK
PCI clock input.
SER_IRQ
PCI_IO
Serial IRQ pin used with the PCI_CLK pin
to transfer LPC47N227 interrupts to the
host.
nIO_PME
(O12/OD12) This active low Power Management Event
signal allows the LPC47N227 to request
wakeup.
FLOPPY DISK INTERFACE
DRVDEN0
(O12/OD12) Indicates the drive and media selected.
Refer to configuration registers CR03,
CR0B, CR1F.
DRVDEN1
(O12/OD12) Indicates the drive and media selected.
Refer to configuration registers CR03,
CR0B, CR1F.
nMTR0
(O12/OD12) These active low output selects motor
drive 0.
nDSKCHG
IS
This input senses that the drive door is
open or that the diskette has possibly been
changed since the last drive selection.
This input is inverted and read via bit 7 of
I/O address 3F7H. The nDSKCHG bit also
depends upon the state of the Force Disk
Change bits in the Force FDD Status
Change configuration register (see
subsection CR17 in the Configuration
section).
5
FPGA/CPLD
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