CMOS SyncBiFIFO
™
256 x 18 x 2 and 512 x 18 x 2
Integrated Device Technology, Inc.
IDT72605
IDT72615
FEATURES:
• Two independent FIFO memories for fully bidirectional
data transfers
• 256 x 18 x 2 organization (IDT 72605)
• 512 x 18 x 2 organization (IDT 72615)
• Synchronous interface for fast (20ns) read and write
cycle times
• Each data port has an independent clock and read/write
control
• Output enable is provided on each port as a three-state
control of the data bus
• Built-in bypass path for direct data transfer between two
ports
• Two fixed flags, Empty and Full, for both the A-to-B and
the B-to-A FIFO
• Programmable flag offset can be set to any depth in the
FIFO
• The synchronous BiFIFO is packaged in a 64-pin TQFP
(Thin Quad Flatpack), 68-pin PGA and 68-pin PLCC
• Industrial temperature range (-40oC to +85oC) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT72605 and IDT72615 are very high-speed, low-
power bidirectional First-In, First-Out (FIFO) memories, with
synchronous interface for fast read and write cycle times. The
SyncBiFIFO™ is a data buffer that can store or retrieve
information from two sources simultaneously. Two Dual-Port
FIFO memory arrays are contained in the SyncBiFIFO; one
data buffer for each direction.
The SyncBiFIFO has registers on all inputs and outputs.
Data is only transferred into the I/O registers on clock edges,
hence the interfaces are synchronous. Each Port has its own
independent clock. Data transfers to the I/O registers are
gated by the enable signals. The transfer direction for each
port is controlled independently by a read/write signal. Individ-
ual output enable signals control whether the SyncBiFIFO is
driving the data lines of a port or whether those data lines are
in a high-impedance state.
Bypass control allows data to be directly transferred from
input to output register in either direction.
The SyncBiFIFO has eight flags. The flag pins are full,
empty, almost-full, and almost-empty for both FIFO memo-
ries. The offset depths of the almost-full and almost-empty
flags can be programmed to any location.
The SyncBiFIFO is fabricated using IDT’s high-speed,
submicron CMOS technology.
FUNCTIONAL BLOCK DIAGRAM
D
A0
-D
A17
R/
W
A
EN
A
OE
A
HIGH
Z
CONTROL
CLK
A
INPUT REGISTER
OUTPUT REGISTER
MUX
MEMORY
ARRAY
512 x 18
256 x 18
MUX
MEMORY
ARRAY
512 x 18
256 x 18
RESET
LOGIC
CS
A
A
2
A
1
A
0
µ
P
INTERFACE
FLAG
LOGIC
RS
EF
BA
PAE
BA
PAF
BA
FF
BA
3
7
EF
AB
PAE
AB
PAF
AB
FF
AB
FLAG
LOGIC
POWER
SUPPLY
INPUT REGISTER
V
CC
GND
CLK
B
OUTPUT REGISTER
HIGH
Z
CONTROL
OE
B
R/
W
B
EN
B
BYP
B
COMMERCIAL TEMPERATURE RANGES
©1996
Integrated Device Technology, Inc.
D
B0
-D
B17
2704 drw 01
SyncBiFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
DECEMBER 1996
DSC-2704/5
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.18
1
IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
11
10
09
D
B1
D
B3
D
B2
D
B0
D
B4
GND
D
B5
D
B6
D
B7
D
B8
D
B9
V
CC
D
B11
D
B13
GND
D
B12
D
B14
D
B15
D
B16
D
B17
GND D
B10
RS
OE
A
08 R/
W
B
CLK
B
07
PAE
AB
PAF
AB
EF
AB
FF
AB
G68-1
A
2
A
0
Pin 1 Designator
OE
B
EN
B
BYP
B
06 GND
05
04
03
02
01
A
V
CC
A
1
PAE
BA
PAF
BA
EF
BA
FF
BA
D
A1
D
A2
D
A0
D
A3
D
A4
B
GND
D
A5
C
D
A6
D
A7
D
D
A8
D
A9
E
GND D
A10
V
CC
F
PGA
Top View
EN
A
CS
A
CLK
A
R/
W
A
D
A12
D
A14
D
A16
D
A13
GND D
A15
H
J
K
L
2704 drw 02
D
A17
D
A11
G
D
A16
D
A17
CLK
A
R/W
A
EN
A
CS
A
A
0
A
1
A
2
V
CC
EF
AB
FF
AB
PAE
AB
PAF
AB
OE
A
D
B17
D
B16
9 8 7 6 5 4 3 2
68 67 66 65 64 63 62 61
1
10
60
11
59
12
58
57
13
56
14
55
15
54
16
53
17
J68-1
52
18
51
19
50
20
49
21
48
22
47
23
46
24
45
25
44
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
D
B15
GND
D
B14
D
B13
D
B12
D
B11
D
B10
V
CC
GND
D
B9
D
B8
D
B7
D
B6
D
B5
GND
D
B4
D
B3
D
A15
GND
D
A14
D
A13
D
A12
D
A11
D
A10
V
CC
GND
D
A9
D
A8
D
A7
D
A6
D
A5
GND
D
A4
D
A3
D
A2
D
A1
D
A0
EF
BA
FF
BA
PAE
BA
PAF
BA
GND
BYP
B
OE
B
EN
B
R/W
B
CLK
B
RS
D
B0
D
B1
D
B2
2704 drw 03
PLCC
Top View
5.18
2
IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
EF
BA
FF
BA
PAE
BA
PAF
BA
BYB
B
OE
B
EN
B
R/
W
B
CLK
B
GND
DA
1
DA
0
DB
0
DB
1
PIN 1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DA
2
DA
3
DA
4
DA
5
DA
6
DA
7
DA
8
DA
9
GND
VCC
DA
10
DA
11
DA
12
DA
13
DA
14
DA
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PN64-1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DB
3
DB
4
GND
DB
5
DB
6
DB
7
DB
8
DB
9
DB
10
DB
11
DB
12
DB
13
DB
14
GND
DB
15
DB
16
R/
W
A
EN
A
CS
A
EF
AB
FF
AB
PAE
AB
PAF
AB
OE
A
A
0
A
1
CLK
A
A
2
DA
16
DA
17
V
CC
RS
DB
17
DB
2
2704 drw 04
TQFP
Top View
5.18
3
IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Symbol
D
A0
-D
A17
Name
Data A
Chip Select A
Read/Write A
I/O
I/O
I
I
Description
Data inputs & outputs for the 18-bit Port A bus.
This pin controls the read or write direction of Port A. If R/
W
A
is LOW, Data A input data is
written into Port A. If R/
W
A
is HIGH, Data A output data is read from Port A. In bypass mode,
when R/
W
A
is LOW, message is written into A→B output register. If R/
W
A
is HIGH, message
is read from B→A output register.
CLK
A
is typically a free running clock. Data is read or written into Port A on the rising edge of
CLK
A
.
When
EN
A
is LOW, data can be read or written to Port A. When
EN
A
is HIGH, no data
transfers occur.
When R/
W
A
is HIGH , Port A is an output bus and
OE
A
controls the high-impedance state of
D
A0
-D
A17
. If
OE
A
is HIGH, Port A is in a high-impedance state. If
OE
A
is LOW while
CS
A
is
LOW and R/
W
A
is HIGH, Port A is in an active (low-impedance) state.
Data inputs & outputs for the 18-bit Port B bus.
This pin controls the read or write direction of Port B. If R/
W
B
is LOW, Data B input data is
written into Port B. If R/
W
B
is HIGH, Data B output data is read from Port B. In bypass mode,
when R/
W
B
is LOW, message is written into B→A output register. If R/
W
B
is HIGH, message
is read from A→B output register.
Clock B is typically a free running clock. Data is read or written into Port B on the rising edge
of CLK
B
.
When
EN
B
is LOW, data can be read or written to Port B. When
EN
B
is HIGH, no data
transfers occur.
When R/
W
B
is HIGH , Port B is an output bus and
OE
B
controls the high-impedance state of
D
B0
-D
B17
. If OE
B
is HIGH, Port B is in a high-impedance state. If
OE
B
is LOW while R/
W
B
is HIGH, Port B is in an active (low-impedance) state.
When
EF
AB
is LOW, the A→B FIFO is empty and further data reads from Port B are inhibited.
When
EF
AB
is HIGH, the FIFO is not empty.
EF
AB
is synchronized to CLK
B
. In the bypass
mode,
EF
AB
HIGH indicates that data D
A0
-D
A17
is available for passing through. After the
data D
B0
-D
B17
has been read,
EF
AB
goes LOW.
Port A is accessed when
CS
A
is LOW. Port A is inactive if
CS
A
is HIGH.
CS
A
R/
W
A
CLK
A
Clock A
Enable A
Output Enable A
I
I
I
EN
A
OE
A
A
0
, A
1
, A
2
Addresses
D
B0
-D
B17
R/
W
B
Data B
Read/Write B
I
I/O
I
When
CS
A
is asserted, A
0
, A
1
, A
2
and R/
W
A
are used to select one of six internal resources.
CLK
B
Clock B
Enable B
Output Enable B
I
I
I
EN
B
OE
B
EF
AB
A→B Empty Flag
O
PAE
AB
A→B
Programmable
Almost-Empty Flag
A→B
Programmable
Almost-Full Flag
A→B Full Flag
O
PAF
AB
When
PAE
AB
is LOW, the A→B FIFO is almost empty. An almost empty FIFO contains less
than or equal to the offset programmed into
PAE
AB
Register. When
PAE
AB
is HIGH, the
A→B FIFO contains more than offset in
PAE
AB
Register. The default offset value for
PAE
AB
Register is 8.
PAE
AB
is synchronized to CLK
B
.
O
FF
AB
When
PAF
AB
is LOW, the A→B FIFO is almost full. An almost full FIFO contains greater than
the FIFO depth minus the offset programmed into
PAF
AB
Register. When PAF
AB
is HIGH,
the A→B FIFO contains less than or equal to the depth minus the offset in PAF
AB
Register.
The default offset value for PAF
AB
Register is 8.
PAF
AB
is synchronized to CLK
A
.
O
When
FF
AB
is LOW, the A→B FIFO is full and further data writes into Port A are inhibited.
When
FF
AB
is HIGH, the FIFO is not full.
FF
AB
is synchronized to CLK
A
. In bypass mode,
FF
AB
tells Port A that a message is waiting in Port B’s output register. If
FF
AB
is LOW, a
bypass message is in the register. If
FF
AB
is HIGH, Port B has read the message and another
message can be written into Port A.
EF
BA
B→A Empty Flag
O
PAE
BA
B→A
Programmable
Almost-Empty Flag
B→A
Programmable
Almost-Full Flag
O
PAF
BA
When
PAE
BA
is LOW, the B→A FIFO is almost empty. An almost empty FIFO contains less
than or equal to the offset programmed into
PAE
BA
Register. When
PAE
BA
is HIGH, the
B→A FIFO contains more than offset in
PAE
BA
Register. The default offset value for
PAE
BA
Register is 8.
PAE
BA
is synchronized to CLK
A
.
When
EF
BA
is LOW, the B→A FIFO is empty and further data reads from Port A are inhibited.
When
EF
BA
is HIGH, the FIFO is not empty.
EF
BA
is synchronized to CLK
A
. In the bypass
mode,
EF
BA
HIGH indicates that data D
B0
-D
B17
is available for passing through. After the
data D
A0
-D
A17
has been read,
EF
BA
goes LOW on the following cycle.
O
When
PAF
BA
is LOW, the B→A FIFO is almost full. An almost full FIFO contains greater than
the FIFO depth minus the offset programmed into
PAF
BA
Register. When
PAF
BA
is HIGH,
the B→A FIFO contains less than or equal to the depth minus the offset in
PAF
BA
Register.
The default offset value for
PAF
BA
Register is 8.
PAF
BA
is synchronized to CLK
B
.
2704 tbl 01
5.18
4
IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (Continued)
Symbol
Name
B→A Full Flag
I/O
O
Description
When
FF
BA
is LOW, the B→A FIFO is full and further data writes into Port B are inhibited.
When
FF
BA
is HIGH, the FIFO is not full.
FF
BA
is synchronized to CLK
B
. In bypass mode,
FF
BA
tells Port B that a message is waiting in Port A’s output register. If
FF
BA
is LOW, a
bypass message is in the register. If
FF
BA
is HIGH, Port A has read the message and another
message can be written into Port B.
This flag informs Port B that the Synchronous BiFIFO is in bypass mode. When BYP
B
is
LOW, Port A has placed the FIFO into bypass mode. If
BYP
B
is HIGH, the Synchronous
BiFIFO passes data into memory.
BYP
B
is synchronized to CLK
B
.
A LOW on this pin will perform a reset of all Synchronous BiFIFO functions.
There are three +5V power pins for the PLCC and PGA packages and two for the TQFP.
There are seven ground pins for the PLCC and PGA packages and four for the TQFP.
2704 tbl 02
FF
BA
BYP
B
RS
V
CC
GND
Port B Bypass
Flag
Reset
Power
Ground
O
I
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
Rating
Terminal Voltage
with Respect
to Ground
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
DC Output Current
Com’l.
–0.5 to +7.0
Mil.
–0.5 to +7.0
Unit
V
RECOMMENDED DC
OPERATING CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
(1)
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Min. Typ. Max. Unit
4.5
0
2.0
—
5.0
0
—
—
5.5
0
—
0.8
V
V
V
V
2704 tbl 04
T
A
T
BIAS
T
STG
I
OUT
0 to +70
–55 to +125
–55 to +125
50
–55 to +125
–65 to +135
–65 to +150
50
°C
°C
°C
mA
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
(2)
C
OUT
(1,2)
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
Unit
10
10
pF
pF
2704 tbl 05
NOTE:
2704 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
NOTES:
1. With output deselected.
2. Characterized values, not currently tested.
DC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5V
±
10%, T
A
= 0°C to +70°C)
IDT72615L
IDT72605L
Commercial
t
CLK
= 20, 25, 35, 50ns
Typ.
—
—
—
—
—
Symbol
I
IL
(1)
I
OL
(2)
V
OH
V
OL
I
CC
(3)
Parameter
Input Leakage Current (Any Input)
Output Leakage Current
Output Logic "1" Voltage I
OUT
= –2mA
Output Logic "0" Voltage I
OUT
= 8mA
Average V
CC
Power Supply Current
Min.
–1
–10
2.4
—
—
Max.
1
10
—
0.4
230
Unit
µA
µA
V
V
mA
2704 tbl 06
NOTES:
1. Measurements with 0.4V
≤
V
IN
≤
V
CC
.
2.
OEA
,
OEB
≥
V
IH
; 0.4
≤
V
OUT
≤
V
CC
.
3. Tested with outputs open. Testing frequency f=20MHz
5.18
5
FPGA/CPLD
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