HD74LV161A
Synchronous 4-bit Binary Counter (Direct Clear)
REJ03D0319–0400Z
(Previous ADE-205-264B (Z))
Rev.4.00
Jun. 04, 2004
Description
The HD74LV161A is 4-bit binary counters. All flip flops are clocked simultaneously on the low to high to transition
(positive edge) of the clock input waveform. These counters may be preset using the load input. Presetting of all four
flip flops is synchronous to the rising edge of clock. When load is held low counting is disabled and the data on the A,
B, C and D inputs is loaded into the counter on the rising edge clock. If the load input is taken high before the positive
edge of clock, the count operation will be unaffected.
Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the
low-power consumption extends the battery life.
Features
•
•
•
•
•
•
•
V
CC
= 2.0 V to 5.5 V operation
All inputs V
IH
(Max.) = 5.5 V (@V
CC
= 0 V to 5.5 V)
All outputs V
O
(Max.) = 5.5 V (@V
CC
= 0 V)
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25°C)
Typical V
OH
undershoot > 2.3 V (@V
CC
= 3.3 V, Ta = 25°C)
Output current ±6 mA (@V
CC
= 3.0 V to 3.6 V), ±12 mA (@V
CC
= 4.5 V to 5.5 V)
Ordering Information
Package Type
SOP–16 pin(JEITA)
SOP–16 pin(JEDEC)
TSSOP–16 pin
Package Code
FP–16DAV
FP–16DNV
TTP–16DAV
Package
Abbreviation
FP
RP
T
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
ELL (2,000 pcs/reel)
Part Name
HD74LV161AFPEL
HD74LV161ARPEL
HD74LV161ATELL
Note: Please consult the sales office for the above package availability.
Rev.4.00 Jun. 04, 2004 page 1 of 15
HD74LV161A
Function Table
Inputs
CLR
L
H
H
H
H
H
LOAD
X
L
H
H
H
X
ENP
X
X
X
L
H
X
ENT
X
X
L
X
H
X
CLK
X
↑
↑
↑
↑
↓
Outputs
QA
L
A
No change
No change
Count up
No change
QB
L
B
QC
L
C
QD
L
D
Note: H: High level
L: Low level
X: Immaterial
↑:
Low to high transition
↓:
High to low transition
A, B, C, D: Data input
Carry = ENT • QA • QB • QC • QD
Pin Arrangement
CLR
1
CK 2
A 3
B 4
C 5
D 6
ENP 7
GND 8
16 V
CC
15 CARRY
OUTPUT
14 QA
13 QB
12 QC
11 QD
10 ENT
9
LOAD
(Top view)
Rev.4.00 Jun. 04, 2004 page 2 of 15
HD74LV161A
Absolute Maximum Ratings
Item
Supply voltage range
Input voltage range*
Output voltage range*
1, 2
Input clamp current
Output clamp current
Continuous output current
Continuous current through
V
CC
or GND
Maximum power dissipation at
Ta = 25°C (in still air)*
3
Storage temperature
1
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
or I
GND
P
T
Tstg
Ratings
–0.5 to 7.0
–0.5 to 7.0
–0.5 to V
CC
+ 0.5
–0.5 to 7.0
–20
±50
±25
±50
785
500
–65 to 150
Unit
V
V
V
mA
mA
mA
mA
mW
°C
Conditions
H or L
Output: H or L
V
CC
: OFF
V
I
< 0
V
O
< 0 or V
O
> V
CC
V
O
= 0 to V
CC
SOP
TSSOP
Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are
observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Recommended Operating Conditions
Item
Supply voltage range
Input voltage range
Output voltage range
Output current
Symbol
V
CC
V
I
V
O
I
OH
Min
2.0
0
0
—
—
—
—
—
—
—
—
0
0
0
–40
Max
5.5
5.5
V
CC
–50
–2
–6
–12
50
2
6
12
200
100
20
85
Unit
V
V
V
µA
mA
Conditions
I
OL
µA
mA
Input transition rise or fall rate
∆t
/∆v
ns/V
V
CC
= 2.0 V
V
CC
= 2.3 to 2.7 V
V
CC
= 3.0 to 3.6 V
V
CC
= 4.5 to 5.5 V
V
CC
= 2.0 V
V
CC
= 2.3 to 2.7 V
V
CC
= 3.0 to 3.6 V
V
CC
= 4.5 to 5.5 V
V
CC
= 2.3 to 2.7 V
V
CC
= 3.0 to 3.6 V
V
CC
= 4.5 to 5.5 V
Operating free-air temperature
Ta
°C
Note: Unused or floating inputs must be held high or low.
Rev.4.00 Jun. 04, 2004 page 3 of 15
HD74LV161A
Logic Diagram
CLK
CLR
LOAD
Enable
P
T
A
D Q
CK
CLR
D Q
CK
CLR
Output
Q
A
Q
Output
Q
B
Q
B
D Q
Output
Q
C
Data
Inputs
CK
CLR
Q
C
D Q
CK
CLR
Output
Q
D
Q
D
Carry
Output
Rev.4.00 Jun. 04, 2004 page 4 of 15
HD74LV161A
Timing Diagram
CLR
LOAD
A
Data
Inputs
B
C
D
CLK
ENP
ENT
Q
A
Out
puts
Q
B
Q
C
Q
D
Carry
12
13
14
15
0
1
2
Count
Clear
Preset
(Load)
Inhibit
Rev.4.00 Jun. 04, 2004 page 5 of 15
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