16 x 16 PARALLEL CMOS
MULTIPLIER-ACCUMULATOR
Integrated Device Technology, Inc.
IDT7210L
FEATURES:
• 16 x 16 parallel multiplier-accumulator with selectable
accumulation and subtraction
• High-speed: 20ns multiply-accumulate time
• IDT7210 features selectable accumulation, subtraction,
rounding and preloading with 35-bit result
• IDT7210 is pin and function compatible with the TRW
TDC1010J, TMC2210, Cypress CY7C510, and AMD
AM29510
• Performs subtraction and double precision addition and
multiplication
• Produced using advanced CMOS high-performance
technology
• TTL-compatible
• Available in topbraze DIP, PLCC, Flatpack and Pin Grid
Array
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing #5962-88733 is listed on this
function
• Speeds available:
Commercial: L20/25/35/45/55/65
Military:
L25/30/40/55/65/75
DESCRIPTION:
The IDT7210 is a high-speed, low-power 16 x 16-bit parallel
multiplier-accumulator that is ideally suited for real-time digital
signal processing applications. Fabricated using CMOS
silicon gate technology, this device offers a very low-power
alternative to existing bipolar and NMOS counterparts, with
only 1/7 to 1/10 the power dissipation and exceptional speed
(25ns maximum) performance.
A pin and functional replacement for TRW’s TDC1010J the
IDT7210 operates from a single 5 volt supply and is compatible
with standard TTL logic levels. The architecture of the IDT7210
is fairly straightforward, featuring individual input and output
registers with clocked D-type flip-flop, a preload capability
which enables input data to be preloaded into the output
registers, individual three-state output ports for the Extended
Product (XTP) and Most Significant Product (MSP) and a
Least Significant Product output (LSP) which is multiplexed
with the Y input.
The X
IN
and Y
IN
data input registers may be specified
through the use of the Two’s Complement input (TC) as either
a two’s complement or an unsigned magnitude, yielding a full-
precision 32-bit result that may be accumulated to a full 35-bit
result. The three output registers – Extended Product (XTP),
Most Most Significant Product (MSP) and Least Significant
Product (LSP) – are controlled by the respective TSX, TSM
and TSL input lines. The LSP output can be routed through Y
IN
ports.
FUNCTIONAL BLOCK DIAGRAM
CLKX
X
IN
(X
15
-X
0
)
16
ACC, SUB,
RND, TC
4
CLKY
Y
IN
(Y
15
-Y
0
/P
15
-P
0
)
16
XREGISTER
CONTROL
REGISTER
MULTIPLIER ARRAY
32
YREGISTER
+
+/–
TSL
PREL
ACCUMULATOR
35
35
CLKP
TSX
3
XTP
OUT
(P
34
-P
32
)
XTP REGISTER
3
MSP REGISTER
LSP REGISTER
16
TSM
PREL
16
MSP
OUT
(P
31
-P
16
)
IDT7210
2577 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995
Integrated Device Technology, Inc.
AUGUST 1995
DSC-2018/7
11.2
1
IDT7210L
16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DESCRIPTION (Continued)
The Accumulate input (ACC) enables the device to perform
either a multiply or a multiply-accumulate function. In the
multiply-accumulate mode, output data can be added to or
subtracted from previous results. When the Subtraction (SUB)
input is active simultaneously with an active ACC, a subtraction
can be performed. The double precision accumulated result is
rounded down to either a single precision or single precision
plus 3-bit extended result. In the multiply mode, the Extended
Product output (XTP) is sign extended in the two’s complement
mode or set to zero in the unsigned mode. The Round (RND)
control rounds up the Most Significant Product (MSP) and the
3-bit Extended Product (XTP) outputs. When Preload input
(PREL) is active, all the output buffers are forced into a high-
impedance state (see Preload truth table) and external data
can be loaded into the output register by using the TSX, TSL
and TSM signals as input controls.
PIN CONFIGURATIONS
X
6
X
5
X
4
X
3
X
2
X
1
X
0
P
0
,
P
1
,
P
2
,
P
3
,
P
4
,
P
5
,
P
6
,
P
7
,
GND
P
8
,
P
9
,
P
10
,
P
11
,
P
12
,
P
13
,
P
14
,
P
15
,
P
16
P
17
P
18
P
19
P
20
P
21
P
22
P
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
C64-2 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
X
7
X
8
X
9
X
10
X
11
X
12
X
13
X
14
X
15
TSL
RND
SUB
ACC
CLKX
CLKY
V
CC
TC
TSX
PREL
TSM
CLKP
P
34
P
33
P
32
P
31
P
30
P
29
P
28
P
27
P
26
P
25
P
24
P
2
, Y
2
P
3
, Y
3
P
4
, Y
4
P
5
, Y
5
P
6
, Y
6
P
7
, Y
7
GND
GND
P
8
, Y
8
P
9
, Y
9
P
10
, Y
10
P
11
, Y
11
P
12
, Y
12
P
13
, Y
13
P
14
, Y
14
P
15
, Y
15
P
16
60 59 58 5756 55 54 53 5251 50 4948 47 46 45 44
P
1
, Y
1 61
P
0
, Y
0 62
X
0 63
X
1 64
X
2 65
X
3 66
X
4 67
X
5 68
X
6 1
X
7 2
X
8 3
X
9 4
X
10 5
X
11 6
X
12 7
X
13 8
X
14 9
J68-1, L68-1
J68-1
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
P
17
P
18
P
19
P
20
P
21
P
22
P
23
P
24
P
25
P
26
P
27
P
28
P
29
P
30
P
31
P
32
P
33
10 11 1213 14 1516 17 18 19 20 21 22 23 24 25 26
2577 drw 03
2577 drw 02
DIP
TOP VIEW
P
0
,
Y
0
X
0
X
1
X
2
X
3
X
4
X
5
X
6
X
7
X
8
X
9
X
10
X
11
X
12
X
13
X
14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64636261 605958575655 545352 515049
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P
1
,
Y
1
P
2
,
Y
2
P
3
,
Y
3
P
4
,
Y
4
P
5
,
Y
5
P
6
,
Y
6
P
7
,
Y
7
GND
P
8
,
Y
8
P
9
,
Y
9
P
10
,
Y
10
P
11
,
Y
11
P
12
,
Y
12
P
13
,
Y
13
P
14
,
Y
14
P
15
,
Y
15
X
15
TSL
RND
SUB
ACC
CLKX
CLKY
V
CC
V
CC
V
CC
V
CC
TC
TSX
PREL
TSM
CLKP
P
34
PLCC
TOP VIEW
F64-1
P
16
P
17
P
18
P
19
P
20
P
21
P
22
P
23
P
24
P
25
P
26
P
27
P
28
P
29
P
30
P
31
17181920 212223242526 272829 303132
2577 drw 04
11.2
X
15
TSL
RND
SUB
ACC
CLKX
CLKY
V
CC
TC
TSX
PREL
TSM
CLKP
P
34
P
33
P
32
FLATPACK
TOP VIEW
2
IDT7210L
16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
11
10
09
08
07
06
05
04
03
02
01
Pin 1
Designator
A
X
13
X
11
X
9
X
7
X
5
X
3
X
1
Y
0,
P
0
NC
NC
X
14
X
12
X
10
X
8
X
6
X
4
X
2
X
0
Y
1,
P
1
Y
2,
P
2
B
X
15
TSL
RND ACC CLK
Y
SUB CLK
X
V
CC
TC PREL CLK
P
P
33
TSX TSM
P
34
P
32
P
30
P
28
P
26
NC
P
31
P
29
P
27
P
25
P
23
P
21
P
19
P
17
G68-2
P
24
P
22
P
20
P
18
Y
3,
P
3
Y
4,
P
4
C
Y
5,
P
5
Y
6,
P
6
D
Y
7,
P
7
GND
E
Y
8,
P
8
Y
9,
P
9
F
Y
10,
P
10
Y
11,
P
11
G
Y
12,
P
12
Y
13,
P
13
H
Y
14,
P
14
Y
15,
P
15
J
P
16
NC
K
L
2577 drw 05
PGA
TOP VIEW
PIN DESCRIPTIONS
Pin Name
X
0
-
15
Y
0 - 15
/ P
0
-
15
P
16
-
31
P
32
-
34
CLKX
CLKY
CLKP
TSX
TSM
TSL
PREL
ACC
I/O
I
I/O
I/O
I/O
I
I
I
I
I
I
I
I
Data Inputs
Multiplexed I/O port. Y
0 - 15
are data inputs and can be used to preload LSP register on PREL = 1. P
0
-
15
are LSP register outputs - enabled by TSL.
MSP register outputs - enabled by TSM. MSP register can be preloaded when PREL = 1.
XTP register outputs - enabled by TSX. XTP register can be preloaded through these inputs when
PREL = 1.
Input data X
0
-
15
loaded in X input register on CLKX rising edge.
Input data Y
0 - 15
loaded in Y input register on CLKY rising edge.
Output data loaded into output register on rising edge of CLKP.
TSX = 0 enables XTP outputs, TSX = 1 tristates P
32
-
34
lines.
TSM = 0 enables MSP outputs, TSM = 1 tristates P
16
-
31
lines.
TSL = 0 enables LSP outputs, TSL = 1 tristates P
0
-
15
lines.
When PREL= 1 data is input on P
0
-
15
lines. When PREL = 0, inputs on these lines are ignored.
This input is loaded into the control register on the rising edge of (CLKX + CLKY).
When ACC = 1 and SUB = 0 an accumulate operation is performed. When ACC = 1 and SUB = 1, a
subtract operation is performed. When ACC = 0, the SUB input is a don't care and the device acts as a
simple multipler with no accumulation
This input is loaded into the control register on the rising edge of (CLKX + CLKY).
This input is active only when ACC = 1. When SUB = 1 the contents of the output register are subtracted
from the result and stored back in the output register. When SUB = 0 the contents of the output register
are added to the result and stored back in the output register
This input is loaded into the control register on the rising edge of (CLKX + CLKY).
When TC = 1, the X and Y input are assumed to be in two's complement form. When TC = 0, X and Y
inputs are assumed to be in unsigned magnitude form
This input is loaded into the control register on the rising edge of (CLKX + CLKY).
RND is inactive when low. RND = 1, adds a "1" to the most significant bit of the LSP, to round MSP and
XTP data
2577 tbl 01
Description
SUB
I
TC
I
RND
I
11.2
3
IDT7210L
16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PRELOAD TRUTH TABLE
PREL
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
TSX
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
TSM
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
TSL
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
XTP
Q
Q
Q
Q
Hi Z
Hi Z
Hi Z
Hi Z
Hi Z
Hi Z
Hi Z
Hi Z
PL
PL
PL
PL
MSP
Q
Q
Hi Z
Hi Z
Q
Q
Hi Z
Hi Z
Hi Z
Hi Z
PL
PL
Hi Z
Hi Z
PL
PL
LSP
Q
Hi Z
Q
Hi Z
Q
Hi Z
Q
Hi Z
Hi Z
PL
Hi Z
PL
Hi Z
PL
Hi Z
PL
NOTES ON TWO'S COMPLEMENT FORMATS
1. In two's complement notation, the location of the binary
point that signifies the separation of the fractional and
integer fileds is just after the sign, between the sign bit
(-2°) and the next significant bit for the multiplier inputs.
This same format is carried over to the output format,
except that the extended significance of the integer filed is
provided to extend the utility of the accumulator. In the
case of the output rotation, the output binary point is
located between the2° and 2
1
bit positions. The location of
the binary point is arbitrary, as long as there is consistency
with both the input and output formats. The number filed
can be considered entirely integer with the binary point just
to the right of the least significant bit for the input, product
and the accumulated sum.
2. When in the non-accumulating mode, the first four bits (P
34
to P
31
) will all indicate the sign of the product. Additionally,
the P
30
term will also indicate the sign with one exception,
when multiplying -1 x -1. With the additional bits that are
available in this multiplier, the –1 x –1 is a valid operation
that yields a +1 product.
3. In operations that require the accumulation of single prod-
ucts or sum of products, there is no change in format. To
allow for a valid summation beyond that available for a
single multiplication product, three additional significant
bits (guard bits) are provided. This is the same as if the
product was accumulated off-chip in a separate 35-bit wide
adder. Taking the sign at the most significant bit position
will guarantee that the largest number field will be used.
When the accumulated sum only occupies the right hand
portion of the accumulator, the sign will be extended into
the lesser significant bit positions.
NOTES:
2577 tbl 02
Hi Z = Output buffers at high impedance (output disabled)
Q = Output buffers at low impedance. Contents of output register will be
transferred to output pins.
PL = Output buffers at high impedance or output disabled. Preload data
supplied externally at output pins will be loaded into the output
register at the rising edge of CLKP.
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
V
CC
Power Supply
Voltage
V
TERM
Terminal Voltage
with Respect to
GND
T
A
Operating
Temperature
T
BIAS
Temperature
Under Bias
T
STG
Storage
Temperature
I
OUT
DC Output
Current
Commercial
-0.5 to +7.0
–0.5 to
V
CC
+0.5V
0 to +70
–55 to +125
–55 to +125
50
Military
-0.5 to +7.0
–0.5 to
V
CC
+0.5V
–55 to +125
–65 to +135
–65 to +150
50
Unit
V
V
°C
°C
°C
mA
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
Parameter
(1)
C
IN
Input Capacitance
C
OUT
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
10
12
Unit
pF
pF
NOTE:
2577 tbl 04
1. This parameter is measured at characterization and not 100%tested.
NOTE:
2577 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect reliability.
11.2
4
IDT7210L
16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5.0V
±
10%, T
A
= 0°C to +70°C; Military: V
CC
= 5V
±
10%, T
A
= –55°C to +125°C)
Commercial
Symbol
Parameter
V
IH
Input High Voltage
V
IL
|I
LI
|
|I
LO
|
V
OH
V
OL(4)
I
OS
I
CC (2)
Input Low Voltage
Input Leakage Current
Output Leakage Current
Output HIGH Voltage
Output LOW Voltage
Output Short Circuit Current
Operating Power Supply Current
Test Conditions
(5)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max., V
IN
= 0V to
V
CC
V
CC
= Max., Outputs Disabled
V
OUT
= 0 to
V
CC
V
CC
= Min., I
OH
= –2.0mA
V
CC
= Min., I
OL
= 4mA
V
CC
= Max., V
0
GND
V
CC
= Max., Outputs Enabled
f= 10MHz
(2)
C
L
= 50 pF
V
IN
≥
V
IH
, V
IN
≤
V
IL
V
IN
≥
V
CC
–0.2V, V
IN
Military
Min.
2.0
—
—
—
2.4
—
-20
—
Typ.
(1)
—
—
—
—
—
—
—
45
Max.
—
0.8
10
10
—
0.4
-100
110
Unit
V
V
µA
µA
V
V
mA
mA
Min.
2.0
—
—
—
2.4
—
-20
—
Typ.
(1)
—
—
—
—
—
—
—
45
Max.
—
0.8
10
10
—
0.4
-100
90
I
CCQ1
I
CCQ2
Quiescent Power Supply Current
Quiescent Power Supply Current
—
—
—
20
4
—
30
10
6
—
—
—
20
4
—
30
12
8
mA
mA
mA/
MHz
≤
0.2V
I
CC
/f
(2,3)
Increase in Power Supply
Current MHz
V
CC
= Max., Outputs Disabled
2577 tbl 05
NOTES:
1. Typical implies V
CC
= 5V and T
A
= +25°C.
2. I
CC
is measured at 10MHz and V
IN
= 0 to 3V. For frequencies greater than 10MHz, the following equation is used for the commercial range:
I
CC
= 90+ 6(f –10)mA, where f = operating frequency in MHz. For the military range, I
CC
= 110 + 8(f –10). f = operating frequency in MHz, f = 1/t
MA
.
3. For frequencies greater than 10MHz, guaranteed by design, not production tested.
4. I
OL
= 4mA for t
MA
> 55ns.
5. For conditions shown as Max. or Min., use appropriate value specified under electrical characteristics.
AC ELECTRICAL CHARACTERISTICS COMMERCIAL
(V
CC
= 5V
±
10%, T
A
= 0° to +70°C)
Symbol
t
MA
t
D
t
ENA
t
DIS
t
S
t
H
t
PW
t
HCL
Parameter
Multiply-Accumulate Time
(2)
Output Delay
(2)
3-State Enable Time
3-State Disable Time
(1)
Input Register Set-up Time
Input Register Hold Time
Clock Pulse Width
Relative Hold Time
7210L20
Min. Max.
2.0 20
2.0 18
—
18
—
18
10
—
3
—
9
—
0
—
7210L25
Min. Max.
2.0 25
2.0 20
–
20
–
20
12
–
3
–
10
–
0
–
7210L35
Min. Max.
2.0 35
2.0 25
–
25
–
25
12
–
3
–
10
–
0
–
7210L45
Min. Max.
2.0 45
2.0 25
–
25
–
25
15
–
3
–
15
–
0
–
7210L55
Min. Max.
2.0 55
2.0 30
–
30
–
30
20
–
3
–
20
–
0
–
7210L65
Min. Max. Unit
2.0 65
ns
2.0 35
ns
–
30
ns
–
30
ns
25
–
ns
3
–
ns
25
–
ns
0
–
ns
2577 tbl 06
NOTES:
1. Transition is measured
±500mV
from steady state voltage.
2. Minimum delays guaranteed but not tested
AC ELECTRICAL CHARACTERISTICS MILITARY
(V
CC
= 5V
±
10%, T
A
= –55° to +125°C)
Symbol
t
MA
t
D
t
ENA
t
DIS
t
S
t
H
t
PW
t
HCL
Parameter
Multiply-Accumulate Time
(2)
Output Delay
(2)
3-State Enable Time
3-State Disable Time
(1)
Input Register Set-up Time
Input Register Hold Time
Clock Pulse Width
Relative Hold Time
7210L25
Min. Max.
2.0 25
2.0 20
—
20
—
20
12
—
3
—
10
—
0
—
7210L30
Min. Max.
2.0 30
2.0 20
–
20
–
20
12
–
3
–
10
–
0
–
7210L40
Min. Max.
2.0 40
2.0 25
–
25
–
25
15
–
3
–
15
–
0
–
7210L55
Min. Max.
2.0 55
2.0 30
–
30
–
25
20
–
3
–
20
–
0
–
7210L65
Min. Max.
2.0 65
2.0 35
–
30
–
30
25
–
3
–
25
–
0
–
7210L75
Min. Max. Unit
2.0 75
ns
2.0 35
ns
–
35
ns
–
30
ns
25
–
ns
3
–
ns
25
–
ns
0
–
ns
2577 tbl 07
NOTES:
1. Transition is measured
±500mV
from steady state voltage.
2. Minimum delays guaranteed but not tested
11.2
5
ARM技术
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
