UBA2014
600 V driver IC for HF fluorescent lamps
Rev. 04 — 16 October 2008
Product data sheet
1. General description
The IC is a monolithic integrated circuit for driving electronically ballasted fluorescent
lamps, with mains voltages up to 277 V (RMS) (nominal value).
The circuit is made in a 650 V Bipolar CMOS DMOS (BCD) power-logic process.
It provides the drive function for the two discrete power MOSFETs.
Besides the drive function, the IC also includes the level-shift circuit, the oscillator
function, a lamp voltage monitor, a current control function, a timer function and
protections.
2. Features
I
I
I
I
I
I
I
I
I
Adjustable preheat time
Adjustable preheat current
Current controlled operating
Single ignition attempt
Adaptive non-overlap time control
Integrated high-voltage level-shift function
Power-down function
Protection against lamp failures or lamp removal
Capacitive mode protection
3. Applications
I
The circuit topology enables a broad range of ballast applications at different mains
voltages for driving lamp types from T8, T5, PLC, T10, T12, PLL and PLT, for example.
NXP Semiconductors
UBA2014
600 V driver IV for HF fluorescent lamps
4. Quick reference data
Table 1.
Quick reference data
V
DD
= 13 V; V
FVDD
−
V
SH
= 13 V; T
amb
= 25
°
C; all voltages are referenced to GND; see test circuit of
Figure 8;
unless
otherwise specified.
Symbol
Start-up state
V
DD(stop)
V
DD(start)
I
DD(start)
oscillator stop supply
voltage
oscillator start supply
voltage
oscillator start-up supply
current
high-side supply voltage
reference voltage
maximum bridge frequency
minimum bridge frequency
output source current
output sink current
preheat voltage
lamp fail voltage
maximum lamp voltage
offset voltage
transconductance
preheat time
LOW-level output voltage
HIGH-level output voltage
V
CSP
= V
CSN
= 0 V to 2.5 V
f = 1 kHz
C
CT
= 330 nF;
R
IREF
= 33 kΩ
V
GH
−
V
SH
= 0 V
V
GH
−
V
SH
= 13 V
V
DD
< V
DD(start)
8.6
12.4
-
9.1
13.0
170
9.6
13.6
200
V
V
µA
Parameter
Conditions
Min
Typ
Max
Unit
High-voltage supply
V
HS
V
VREF
f
max
f
min
I
o(source)
I
o(sink)
V
ph
V
lamp(fail)
V
lamp(max)
V
offset
g
m
Preheat timer
t
ph
V
OL
V
OH
1.6
-
-
1.8
1.4
3.6
2.0
-
-
s
V
V
I
HS
< 30
µA
I
L
= 10
µA
-
2.86
90
38.9
135
265
0.57
0.77
1.44
−2
1900
-
2.95
100
40.5
180
330
0.60
0.81
1.49
0
3800
570
3.04
110
42.1
235
415
0.63
0.85
1.54
+2
5700
V
V
kHz
kHz
mA
mA
V
V
V
mV
µA/mV
Reference voltage
Voltage controlled oscillator
High-side output driver
Preheat current sensor
Lamp voltage sensor
Average current sensor
5. Ordering information
Table 2.
Ordering information
Package
Name
UBA2014T
UBA2014P
SO16
DIP16
Description
plastic small outline package; 16 leads; body width 3.9 mm
plastic dual in-line package; 16 leads (300 mil); long body
Version
SOT109-1
SOT38-1
Type number
UBA2014_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 16 October 2008
2 of 19
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6. Block diagram
V
DD
7
3V
9
FV
DD
V
pd
BOOTSTRAP
LEVEL
SHIFTER
GH
SH
GL
11
LS
DRIVER
6
HS
DRIVER
10
reference
voltages
supply (5 V)
14
VREF
UBA2014_4
Rev. 04 — 16 October 2008
STATE LOGIC
ANT/CMD
LOGIC
COUNTER
LOGIC
LAMP
VOLTAGE
SENSOR
15
16
CSP
CSN
AVERAGE
CURRENT
SENSOR
V
lamp(fail)
V
lamp(max)
FREQUENCY
CONTROL
VOLTAGE
CONTROLLED
OSCILLATOR
REFERENCE
CURRENT
I
V
4
3
13
LVS
LOGIC
Product data sheet
UBA2014
V
DD(L)
DRIVER
LOGIC
reset
12
ACM
NXP Semiconductors
SUPPLY
digital
analog
GND
5
PREHEAT TIMER
•
reset state
•
start-up state
•
preheat state
•
ignition state
•
burn state
•
hold state
•
power-down state
PCS
8
PCS
CT
1
2
mgw579
IREF
CF
CSW
© NXP B.V. 2008. All rights reserved.
Fig 1.
Block diagram
600 V driver IV for HF fluorescent lamps
UBA2014
3 of 19
NXP Semiconductors
UBA2014
600 V driver IV for HF fluorescent lamps
7. Pinning information
7.1 Pinning
CT
CSW
CF
IREF
GND
GL
V
DD
PCS
1
2
3
4
16 CSN
15 CSP
14 VREF
13 LVS
CT
CSW
CF
IREF
GND
GL
V
DD
PCS
1
2
3
4
16 CSN
15 CSP
14 VREF
13 LVS
UBA2014T
5
6
7
8
001aad405
UBA2014P
5
6
7
8
001aad486
12 ACM
11 SH
10 GH
9
FV
DD
12 ACM
11 SH
10 GH
9
FV
DD
Fig 2.
Pin configuration (SO16)
Fig 3.
Pin configuration (DIP16)
7.2 Pin description
Table 3.
Symbol
CT
CSW
CF
IREF
GND
GL
V
DD
PCS
FV
DD
GH
SH
ACM
LVS
VREF
CSP
CSN
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
preheat timer output
input of voltage controlled oscillator
voltage controlled oscillator output
internal reference current input
ground
gate output for the low-side switch
low-voltage supply
preheat current sensor input
floating supply voltage; supply for high-side switch
gate output for the high-side switch
source for the high-side switch
capacitive mode input
lamp voltage sensor input
reference voltage output
positive input for the average current sensor
negative input for the average current sensor
UBA2014_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 16 October 2008
4 of 19
NXP Semiconductors
UBA2014
600 V driver IV for HF fluorescent lamps
8. Functional description
8.1 Start-up state
Initial start-up can be achieved by charging the low-voltage supply capacitor C7
(see
Figure 8)
via an external start-up resistor. Start-up of the circuit is achieved under the
condition that both half bridge transistors TR1 and TR2 are non-conductive. The circuit
will be reset in the start-up state. If the low-voltage supply (V
DD
) reaches the value of
V
DD(start)
the circuit will start oscillating. A DC reset circuit is incorporated in the High-Side
(HS) driver. Below the lockout voltage at the FV
DD
pin the output voltage (V
GH
−
V
SH
) is
zero. The voltages at pins CF and CT are zero during the start-up state.
8.2 Oscillation
The internal oscillator is a Voltage Controlled Oscillator (VCO) circuit which generates a
sawtooth waveform between the V
CF(high)
level and 0 V. The frequency of the sawtooth is
determined by capacitor C
CF
, resistor R
IREF
, and the voltage at pin CSW. The minimum
and maximum switching frequencies are determined by R
IREF
and C
CF
; their ratio is
internally fixed. The sawtooth frequency is twice the half bridge frequency. The UBA2014
brings the transistors TR1 and TR2 into conduction alternately with a duty cycle of
approximately 50 %. An overview of the oscillator signal and driver signals is illustrated in
Figure 4.
The oscillator starts oscillating at f
max
. During the first switching cycle the
Low-Side (LS) transistor is switched on. The first conducting time is made extra long to
enable the bootstrap capacitor to charge.
8.3 Adaptive non-overlap
The non-overlap time is realized with an Adaptive Non-overlap circuiT (ANT). By using an
adaptive non-overlap circuit, the application can determine the duration of the non-overlap
time and make it optimum for each frequency; see
Figure 4.
The non-overlap time is
determined by the slope of the half bridge voltage, and is detected by the signal across
resistor R16 which is connected directly to pin ACM. The minimum non-overlap time is
internally fixed. The maximum non-overlap time is internally fixed at approximately 25 %
of the bridge period time. An internal filter of 30 ns is included at the ACM pin to increase
the noise immunity.
8.4 Timing circuit
A timing circuit is included to determine the preheat time and the ignition time. The circuit
consists of a clock generator and a counter.
The preheat time is defined by C
CT
and R
IREF
and consists of 7 pulses at C
CT
; the
maximum ignition time is 1 pulse at C
CT
. The timing circuit starts operating after the
start-up state, as soon as the low supply voltage (V
DD
) has reached V
DD(start)
or when a
critical value of the lamp voltage (V
lamp(fail)
) is exceeded. When the timer is not operating
C
CT
is discharged to 0 V at 1 mA.
UBA2014_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 16 October 2008
5 of 19
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