January 2001
Si4925DY
Dual P-Channel, Logic Level, PowerTrench
®
MOSFET
General Description
These P-Channel Logic Level MOSFETs are produced
using Fairchild Semiconductor's advanced PowerTrench
process that has been especially tailored to minimize the
on-state resistance and yet maintain low gate charge for
superior switching performance.
These devices are well suited for notebook computer
applications: load switching and power management,
battery charging circuits, and DC/DC conversion.
Features
-6 A, -30 V. R
DS(ON)
= 0.032
Ω
@ V
GS
= -10 V,
R
DS(ON)
= 0.045
Ω
@ V
GS
= -4.5 V.
Low gate charge (14.5nC typical).
High performance trench technology for extremely low
R
DS(ON)
.
High power and current handling capability.
SOT-23
SuperSOT
TM
-6
SuperSOT
TM
-8
SO-8
SOT-223
SOIC-16
D2
D1
D1
D2
5
4
3
2
1
2
49
5
6
SO-8
pin
1
S1
G1
S2
G2
7
8
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
P
D
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current - Continuous
- Pulsed
T
A
= 25
o
C unless otherwise noted
Si4925DY
-30
±20
(Note 1a)
Units
V
V
A
-6
-20
2
Power Dissipation for Dual Operation
Power Dissipation for Single Operation
(Note 1a)
(Note 1b)
(Note 1c)
W
1.6
1
0.9
-55 to 150
°C
T
J
,T
STG
R
θ
JA
R
θ
JC
Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
78
40
°C/W
°C/W
© 2001 Fairchild Semiconductor International
Si4925DY Rev.A
Electrical Characteristics
(T
A
= 25
O
C unless otherwise noted )
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
Drain-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Zero Gate Voltage Drain Current
V
GS
= 0 V, I
D
= -250 µA
I
D
= -250 µA, Referenced to 25
o
C
V
DS
= -24 V, V
GS
= 0 V
T
J
= 55°C
I
GSSF
I
GSSR
V
GS(th)
Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse
(Note 2)
-30
-21
-1
-10
100
-100
-1
o
V
mV/
o
C
µA
µA
nA
nA
V
mV/
o
C
0.032
0.051
0.045
A
16
1540
400
170
S
pF
pF
pF
24
35
75
30
20
ns
ns
ns
ns
nC
nC
nC
-1.3
A
V
∆
BV
DSS
/
∆
T
J
I
DSS
V
GS
= 16 V, V
DS
= 0 V
V
GS
= -16 V, V
DS
= 0 V
V
DS
= V
GS
, I
D
= -250 µA
I
D
= 250 µA, Referenced to 25 C
V
GS
= -10 V, I
D
= -6 A
T
J
=125°C
V
GS
= -4.5 V, I
D
= -5 A
-1.7
4
0.025
0.033
0.034
-20
ON CHARACTERISTICS
Gate Threshold Voltage
Gate Threshold Voltage Temp. Coefficient
Static Drain-Source On-Resistance
-3
∆
V
GS(th)
/
∆
T
J
R
DS(ON)
Ω
I
D(ON)
g
FS
C
iss
C
oss
C
rss
t
D(on)
t
r
t
D(off)
t
f
Q
g
Q
gs
Q
gd
I
S
V
SD
Notes:
On-State Drain Current
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
(Note 2)
V
GS
= -10 V, V
DS
= -5 V
V
DS
= -10 V, I
D
= -6 A
V
DS
= -15 V, V
GS
= 0 V,
f = 1.0 MHz
DYNAMIC CHARACTERISTICS
SWITCHING CHARACTERISTICS
Turn - On Delay Time
Turn - On Rise Time
Turn - Off Delay Time
Turn - Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DS
= -15 V, I
D
= -1 A
V
GEN
= -10 V, R
GEN
= 6
Ω
13
22
47
18
V
DS
= -10 V, I
D
= -6 A,
V
GS
= -5 V
14.5
4
5
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
Maximum Continuous Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= -1.3 A
(Note 2)
-0.73
-1.2
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θ
JC
is guaranteed by
design while R
θ
CA
is determined by the user's board design.
a. 78
O
C/W on a 0.5 in
2
pad of 2oz copper.
b. 125
O
C/W on a 0.02 in
2
pad of 2oz copper.
c. 135
O
C/W on a 0.003 in
2
pad of 2oz copper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
Si4925DY Rev.A
Typical Electrical Characteristics
30
- I
D
, DRAIN-SOURCE CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
V
GS
= -10V
-6.0V
2.5
-4.5V
R
DS(ON)
, NORMALIZED
24
2
V
GS
= -3.5V
18
-3.5V
-4.0 V
1.5
-4.5 V
-5.5 V
-7.0 V
12
-3.0V
6
1
-10V
0
0.5
0
1
-V
DS
2
3
4
5
0
6
, DRAIN-SOURCE VOLTAGE (V)
12
18
- I
D
, DRAIN CURRENT (A)
24
30
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Dain Current and Gate Voltage.
0.1
R
DS(ON)
, ON-RESISTANCE (OHM)
1.6
DRAIN-SOURCE ON-RESISTANCE
1.4
I
D
= -6A
V
GS
= -10V
I
D
= -3A
0.08
R
DS(ON)
, NORMALIZED
1.2
0.06
1
0.04
TA = 125°C
25° C
0.8
0.02
0.6
-50
-25
0
25
50
75
100
125
150
0
2
T
J
, JUNCTION TEMPERATURE (° C)
4
6
8
- V
GS
, GATE TO SOURCE VOLTAGE (V)
10
Figure 3. On-Resistance Variation
Temperature.
30
with
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
30
V
DS
= -5.0V
- I
D
, DRAIN CURRENT (A)
24
T
J
= -55° C
25° C
125° C
- I
S
, REVERSE DRAIN CURRENT (A)
10
V
GS
= 0V
TJ = 125° C
25° C
1
18
0.1
-55° C
12
6
0.01
0
1.5
0.001
2
2.5
3
3.5
4
4.5
0
0.3
0.6
0.9
1.2
1.5
- V
GS
, GATE TO SOURCE VOLTAGE (V)
- V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics.
Figure 6. Body Diode Forward Voltage
Variation with Source Current
and Temperature.
Si4925DY Rev.A
Typical Electrical Characteristics
(continued)
10
- V
GS
, GATE-SOURCE VOLTAGE (V)
3000
I
D
= -6A
8
V
DS
= -5V
CAPACITANCE (pF)
2000
Ciss
-10V
-15V
1000
6
500
Coss
4
2
200
f = 1 MHz
V
GS
= 0 V
0.2
0.5
1
2
5
Crss
0
0
6
12
18
24
30
Q
g
, GATE CHARGE (nC)
100
0.1
10
20
30
- V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics.
Figure 8. Capacitance Characteristics.
30
10
- I
D
, DRAIN CURRENT (A)
3
IT
LIM
N)
(O
S
RD
10
1m
10m
0u
30
s
25
20
15
10
5
0
0.01
s
s
0.5
0.05
V
GS
= -10V
SINGLE PULSE
R
θ
JA
=135°C/W
T
A
= 25°C
0.3
1
2
DC
1s
10s
0.01
0.1
5
10
30
50
POWER (W)
10
s
SINGLE PULSE
R
θ
JA
=135°C/W
T
A
= 25°C
0m
0.1
0.5
10
50 100
300
- V
DS
, DRAIN-SOURCE VOLTAGE (V)
SINGLE PULSE TIME (SEC)
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum Power
Dissipation.
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
0.0001
0.001
0.01
0.1
t
1
, TIME (sec)
1
D = 0.5
0.2
0.1
0.05
0.02
0.01
Single Pulse
P(pk)
R
θ
JA
(t) = r(t) * R
θ
JA
R
JA
= 135°C/W
θ
t
1
t
2
T
J
- T
A
= P * R
θ
JA(t)
Duty Cycle, D = t
1
/t
2
10
100
300
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1c.
Transient thermal response will change depending on the circuit board design.
Si4925DY Rev.A
SOIC-8 Tape and Reel Data
SOIC(8lds) Packaging
Configuration:
Figure 1.0
Packaging Description:
EL ECT ROST AT IC
SEN SIT IVE DEVICES
DO NO T SHI P OR STO RE N EAR ST RO NG EL ECT ROST AT IC
EL ECT RO M AGN ETI C, M AG NET IC O R R ADIO ACT IVE FI ELD S
TNR D ATE
PT NUMB ER
PEEL STREN GTH MIN ___ __ ____ __ ___gms
MAX ___ ___ ___ ___ _ gms
Antistatic Cover Tape
ESD Label
SOIC-8 parts are shipped in tape. The carrier tape is
made from a dissipative (carbon filled) polycarbonate
resin. The cover tape is a multilayer film (Heat Activated
Adhesive in nature) primarily composed of polyester film,
adhesive layer, sealant, and anti-static sprayed agent.
These reeled parts in standard option are shipped with
2,500 units per 13" or 330cm diameter reel. The reels are
dark blue in color and is made of polystyrene plastic (anti-
static coated). Other option comes in 500 units per 7" or
177cm diameter reel. This and some other options are
further described in the Packaging Information table.
These full reels are individually barcode labeled and
placed inside a standard intermediate box (illustrated in
figure 1.0) made of recyclable corrugated brown paper.
One box contains two reels maximum. And these boxes
are placed inside a barcode labeled shipping box which
comes in different sizes depending on the number of parts
shipped.
Static Dissipative
Embossed Carrier Tape
F63TNR
Label
Customized
Label
F852
NDS
9959
F852
NDS
9959
F852
NDS
9959
F852
NDS
9959
F852
NDS
9959
SOIC (8lds) Packaging Information
Pin 1
D84Z
TNR
500
Packaging Option
Packaging type
Qty per Reel/Tube/Bag
Standard
(no flow code)
TNR
2,500
L86Z
Rail/Tube
95
F011
TNR
4,000
SOIC-8 Unit Orientation
Reel Size
Box Dimension (mm)
Max qty per Box
Weight per unit (gm)
Weight per Reel (kg)
13" Dia
343x64x343
5,000
0.0774
0.6060
-
530x130x83
30,000
0.0774
-
13" Dia
343x64x343
8,000
0.0774
0.9696
7" Dia
184x187x47
1,000
0.0774
0.1182
Note/Comments
343mm x 342mm x 64mm
Standard Intermediate box
ESD Label
F63TNR Label sample
LOT: CBVK741B019
FSID: FDS9953A
QTY: 2500
SPEC:
F63TNLabel
F63TN Label
ESD Label
(F63TNR)3
D/C1: D9842
D/C2:
QTY1:
QTY2:
SPEC REV:
CPN:
N/F: F
SOIC(8lds) Tape Leader and Trailer
Configuration:
Figure 2.0
Carrier Tape
Cover Tape
Components
Trailer Tape
640mm minimum or
80 empty pockets
Leader Tape
1680mm minimum or
210 empty pockets
©2000 Fairchild Semiconductor International
July 1999, Rev. B
stm32/stm8
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