74LVT574; 74LVTH574
3.3 V octal D-type flip-flop; 3-state
Rev. 04 — 11 September 2008
Product data sheet
1. General description
The 74LVT574; 74LVTH574 is a high-performance product designed for V
CC
operation at
3.3 V.
This device is an 8-bit, edge triggered register coupled to eight 3-state output buffers. The
two sections of the device are controlled independently by the clock (pin CP) and output
enable (pin OE) control gates. The state of each D input (one setup time before the
LOW-to-HIGH clock transition) is transferred to the corresponding flip-flops Q output.
The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS
memories, or MOS microprocessors.
The active LOW output enable (pin OE) controls all eight 3-state buffers independent of
the clock operation.
When pin OE is LOW, the stored data appears at the outputs. When pin OE is HIGH, the
outputs are in the high-impedance OFF-state, which means they will neither drive nor load
the bus.
2. Features
I
I
I
I
I
I
I
I
I
I
I
Inputs and outputs arranged for easy interfacing to microprocessors
3-state outputs for bus interfacing
Common output enable control
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
Live insertion and extraction permitted
No bus current loading when output is tied to 5 V bus
Power-up reset
Power-up 3-state
Latch-up protection
N
JESD78 class II exceeds 500mA
I
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
I
Specified from
−40 °C
to +85
°C
NXP Semiconductors
74LVT574; 74LVTH574
3.3 V octal D-type flip-flop; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74LVT574D
74LVTH574D
74LVT574DB
74LVTH574DB
74LVT574PW
74LVTH574PW
74LVT574BQ
−40 °C
to +85
°C
DHVQFN20
−40 °C
to +85
°C
TSSOP20
−40 °C
to +85
°C
SSOP20
−40 °C
to +85
°C
SO20
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
Version
SOT163-1
SOT339-1
SOT360-1
Type number
plastic dual in-line compatible thermal enhanced very SOT764-1
thin quad flat package; no leads; 20 terminals;
body 2.5
×
4.5
×
0.85 mm
4. Functional diagram
1
11
2
3
4
5
6
7
8
9
CP
D0
D1
D2
D3
D4
D5
D6
D7
OE
1
mna798
EN2
C1
19
18
17
16
15
14
13
12
001aae466
11
19
18
17
16
15
14
13
12
6
7
8
9
2
3
4
5
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1D
2
Fig 1.
Logic symbol
D0
D1
D2
D3
Fig 2.
D4
IEC logic symbol
D5
D6
D7
D
D
D
D
D
D
D
D
CP
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
001aae467
Fig 3.
Logic diagram
© NXP B.V. 2008. All rights reserved.
74LVT_LVTH574_4
Product data sheet
Rev. 04 — 11 September 2008
2 of 16
NXP Semiconductors
74LVT574; 74LVTH574
3.3 V octal D-type flip-flop; 3-state
5. Pinning information
5.1 Pinning
74LVT574
74LVTH574
terminal 1
index area
20 V
CC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
GND
(1)
GND 10
CP 11
13 Q6
12 Q7
OE
2
3
4
5
6
7
8
9
1
D0
D1
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 CP
001aae758
74LVT574
74LVTH574
D2
D3
D4
D5
D6
D7
GND 10
001aah711
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input
Fig 4.
Pin configuration for SO20, and (T)SSOP20
Fig 5.
Pin configuration for DHVQFN20
5.2 Pin description
Table 2.
Symbol
OE
D0 to D7
GND
CP
Q0 to Q7
V
CC
Pin description
Pin
1
2, 3, 4, 5, 6, 7, 8, 9
10
11
19, 18, 17, 16, 15, 14, 13, 12
20
Description
output enable input (active LOW)
data input
ground (0 V)
clock pulse input (active rising edge)
data output
supply voltage
74LVT_LVTH574_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 11 September 2008
3 of 16
NXP Semiconductors
74LVT574; 74LVTH574
3.3 V octal D-type flip-flop; 3-state
6. Functional description
6.1 Function table
Table 3.
Function table
[1]
Control
OE
Load and read register
Hold
Disable outputs
[1]
Operating mode
Input
CP
↑
NC
X
Dn
l
h
X
X
Internal register Output
Qn
L
H
NC
NC
L
H
NC
Z
L
L
H
H = HIGH voltage level;
L = LOW voltage level;
↑
= LOW-to-HIGH clock transition;
h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition;
l = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition;
Z = high-impedance OFF-state;
NC = no change;
X = don’t care.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
stg
T
j
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
storage temperature
junction temperature
total power dissipation
Conditions
[1]
Min
−0.5
−0.5
−0.5
-
-
-
-
−65
[2]
Max
+4.6
+7.0
+7.0
−50
−50
128
−64
+150
150
500
Unit
V
V
V
mA
mA
mA
mA
°C
°C
mW
output in OFF-state or HIGH-state
V
I
< 0 V
V
O
< 0 V
output in LOW-state
output in HIGH-state
[1]
-
-
T
amb
= -40 ˚C to +85 ˚C
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability.
For SO20 packages: above 70 ˚C derate linearly with 8 mW/K.
For SSOP20 and TSSOP20 packages: above 60 ˚C derate linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60 ˚C derate linearly with 4.5 mW/K.
74LVT_LVTH574_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 11 September 2008
4 of 16
NXP Semiconductors
74LVT574; 74LVTH574
3.3 V octal D-type flip-flop; 3-state
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
T
amb
∆t/∆V
Recommended operating conditions
Parameter
supply voltage
input voltage
HIGH-level input voltage
LOW-level input voltage
HIGH-level output current
LOW-level output current
current duty cycle
≤
50 %; f
i
≥
1 kHz
ambient temperature
input transition rise and fall rate
in free air
outputs enabled
Conditions
Min
2.7
0
2.0
-
-
-
-
−40
-
Max
3.6
5.5
-
0.8
−32
32
64
+85
10
Unit
V
V
V
V
mA
mA
mA
°C
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IK
V
OH
input clamping voltage
Conditions
V
CC
= 2.7 V; I
IK
=
−18
mA
V
CC
= 2.7 V; I
OH
=
−8
mA
V
CC
= 3.0 V; I
OH
=
−32
mA
V
OL
LOW-level output voltage
V
CC
= 2.7 V
I
OL
= 100
µA
I
OL
= 24 mA
V
CC
= 3.0 V
I
OL
= 16 mA
I
OL
= 32 mA
I
OL
= 64 mA
V
OL(pu)
I
I
power-up LOW-level
output voltage
input leakage current
V
CC
= 3.6 V; I
O
= 1 mA; V
I
= GND or V
CC
all input pins; V
CC
= 0 V or 3.6 V; V
I
= 5.5 V
control pins; V
CC
= 3.6 V; V
I
= V
CC
or GND
data pins; V
CC
= 3.6 V
V
I
= V
CC
V
I
= 0 V
I
OFF
I
LO
I
BHL
I
BHH
I
BHHO
power-off leakage current V
CC
= 0 V; V
I
or V
O
= 0 V to 4.5 V
output leakage current
bus hold LOW current
bus hold HIGH current
bus hold HIGH
overdrive current
V
O
= 5.5 V and V
CC
= 3.0 V; output HIGH
V
CC
= 3.0 V; V
I
= 0.8 V
V
CC
= 3.0 V; V
I
= 2.0 V
V
CC
= 3.6 V; V
I
= 0V to 3.0 V
[4]
[4]
[4]
[3]
[2]
T
amb
=
−40 °C
to +85
°C
Min
−1.2
2.4
2.0
-
-
-
-
-
-
-
-
-
−5
-
-
75
-
-
Typ
[1]
−0.9
2.5
2.2
0.1
0.3
0.25
0.3
0.4
0.13
1
±0.1
0.1
−1
1
60
150
−150
-
Max
-
-
-
-
0.2
0.5
0.4
0.5
0.55
0.55
10
±1
1
-
±100
125
-
−75
500
Unit
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
µA
HIGH-level output voltage V
CC
= 2.7 V to 3.6 V; I
OH
=
−100 µA
V
CC
−
0.2 V
CC
−
0.1
74LVT_LVTH574_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 11 September 2008
5 of 16
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