CY25562
Spread Spectrum Clock Generator
Spread Spectrum Clock Generator
Features
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■
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50 to 200 MHz operating frequency range
Wide range of spread selections: 9
Accepts clock and crystal inputs
Low power dissipation
❐
70 mW Typ (Fin = 65 MHz)
Frequency spread disable function
Center spread modulation
Low cycle-to-cycle jitter
8-pin SOIC package
This reduction in radiated energy can significantly reduce the
cost of complying with regulatory requirements and time to
market without degrading system performance.
CY25562 is a simple and versatile device. The frequency and
spread percentage range is selected by programming S0 and S1
digital inputs. These inputs use three logic states including high
(H), low (L), and middle (M) logic levels to select one of the nine
available spread percentage ranges. Refer to
Figure 2
on page
4 for programming details.
CY25562 is intended for applications with a reference frequency
in the range of 50 to 200 MHz.
A wide range of digitally selectable spread percentages is made
possible by using the tri-level (high, low, and middle) logic at the
S0 and S1 digital control inputs.
The output spread (frequency modulation) is symmetrically
centered on the input frequency.
Spread spectrum clock control (SSCC) function enables or
disables the frequency spread and is provided for easy
comparison of system performance during EMI testing.
CY25562 is available in an eight-pin SOIC package with a 0 to
70 °C operating temperature range.
Refer to CY25561 for applications with lower drive requirements
and CY25560 with lower drive and frequency requirements.
For a complete list of related documentation, click
here.
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Functional Description
CY25562 is a spread spectrum clock generator (SSCG) IC used
to reduce electromagnetic interference (EMI) found in today’s
high speed digital electronic systems.
CY25562 uses a Cypress proprietary phase locked loop (PLL)
and spread spectrum clock (SSC) technology to synthesize and
frequency modulate the input frequency of the reference clock.
By doing this, the measured EMI at the fundamental and
harmonic frequencies of clock (SSCLK) is reduced.
Logic Block Diagram
300K
X
IN
/
1
CLK
REFERENCE
DIVIDER
PD
CP
Loop
Filter
XOUT 8
MODULATION
CONTROL
FEEDBACK
DIVIDER
vco
V
DD
2
INPUT
DECODER
LOGIC
V
DD
V
DD
DIVIDER
&
MUX
4
SSCLK
V
SS
3
20 K
20 K
20 K
V
SS
20 K
V
SS
5
SSCC
6
S1
7
S0
Cypress Semiconductor Corporation
Document Number: 38-07392 Rev. *I
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 20, 2017
CY25562
Contents
Pinout ................................................................................
Pin Description .................................................................
Functional Overview ........................................................
Frequency and Spread Percentage Selection.............
Trilevel Logic ...............................................................
SSCG Theory of Operation .........................................
CY25562 Application Schematic .....................................
Absolute Maximum Ratings ............................................
Electrical Characteristics.................................................
Thermal Resistance..........................................................
XIN/CLK DC Specification................................................
Electrical Timing Characteristics....................................
Ordering Information........................................................
Ordering Code Definitions ...........................................
3
3
4
4
4
4
6
7
7
7
8
8
9
9
Package Drawing and Dimensions ...............................
Acronyms ........................................................................
Document Conventions .................................................
Units of Measure .......................................................
Document History Page .................................................
Sales, Solutions, and Legal Information ......................
Worldwide Sales and Design Support.......................
Products ....................................................................
PSoC® Solutions ......................................................
Cypress Developer Community.................................
Technical Support .....................................................
10
11
11
11
12
13
13
13
13
13
13
Document Number: 38-07392 Rev. *I
Page 2 of 13
CY25562
Pinout
Figure 1. 8-pin SOIC Pinout
X
IN
/CLK 1
V
DD
2
8 X
OUT
7 S0
CY25562
V
SS
3
SSCLK 4
6 S1
5 SSCC
Pin Description
Pin #
1
2
3
4
5
6
Pin Name
X
IN
/CLK
V
DD
V
SS
SSCLK
SSCC
S1
Type
I
P
P
O
I
I
Pin Description
Clock or crystal connection input. Refer to
Figure 2
on page 4 for input frequency range
selection.
Positive power supply
Power supply ground
SSCG modulated clock output
Spread spectrum clock control (enable/disable) function. SSCG function is enabled when input
is high and disabled when input is low. This pin is pulled high internally.
Tri-level logic input control pin used to select frequency and bandwidth. Frequency/bandwidth
selection and tri-level logic programming. See
Figure 3
on page 4. Pin 6 has internal resistor
divider network to V
DD
and V
SS
. Refer to
Logic Block Diagram
on page 1.
Tri-level logic input control pin used to select frequency and bandwidth. Frequency/bandwidth
selection and tri-level logic programming. See
Figure 3
on page 4. Pin 7 has internal resistor
divider network to V
DD
and V
SS
. Refer to
Logic Block Diagram
on page 1.
Oscillator output pin connected to crystal. Leave this pin unconnected If an external clock
drives X
IN
/CLK.
7
S0
I
8
X
OUT
O
Document Number: 38-07392 Rev. *I
Page 3 of 13
CY25562
Functional Overview
Frequency and Spread Percentage Selection
Figure 2. Frequency and Spread Percentage Selection (Center Spread)
5 0 – 1 0 0 M H z (L o w R a n g e )
In p u t
F re q u e n c y
(M H z )
50 - 60
60 - 70
70 - 80
80 - 100
S1=M
S0=M
(% )
4 .3
4 .0
3 .8
3 .5
S1=M
S0=0
(% )
3 .9
3 .6
3 .4
3 .1
S1=1
S0=0
(% )
3 .3
3 .1
2 .9
2 .7
S1=0
S0=0
(% )
2 .9
2 .6
2 .5
2 .2
S1=0
S0=M
(% )
2 .7
2 .5
2 .4
2 .1
S e le c t th e
F req u e n c y a n d
C e n te r S p re a d %
d e s ire d a n d th e n
set S1, S0 as
in d ic a te d .
1 0 0 – 2 0 0 M H z (H ig h R a n g e )
In p u t
F re q u e n c y
(M H z )
100 – 120
1 2 0 -1 3 0
130 - 140
140 - 150
150 - 160
160 - 170
170 - 180
180 - 190
190 - 200
S1=1
S0=M
(% )
3 .0
2 .7
2 .6
2 .6
2 .5
2 .4
2 .4
2 .3
2 .3
S1=0
S0=1
(% )
2 .4
2 .1
2 .0
2 .0
1 .8
1 .8
1 .8
1 .7
1 .6
S1=1
S0=1
(% )
1 .6
1 .4
1 .3
1 .3
1 .2
1 .2
1 .2
1 .1
1 .1
S1=M
S0=1
(% )
1 .3
1 .1
1 .1
1 .1
1 .0
1 .0
1 .0
0 .9
0 .9
S e le c t th e
F req u e n c y a n d
C e n te r S p re a d %
d e s ire d a n d th e n
set S1, S0 as
in d ic a te d .
Trilevel Logic
With binary logic, four states can be programmed with two control lines, whereas tri-level logic can program nine logic states using
two control lines. Trilevel logic in CY25562 is implemented by defining a third logic state in addition to the standard logic “1” and “0.”
Pins six and seven of CY25562 recognize a logic state by the voltage applied to the respective pin. These states are defined as “0”
(low), “M” (middle), and “1” (one). Each of these states have a defined voltage range that is interpreted by CY25562 as “0”, “M,” or “1”
logic state. Refer to
Electrical Characteristics
on page 7 for voltage ranges for each logic state. CY25562 has two equal value resistors
connected internally to pin 6 and pin 7, which produce the default “M” state. Pins 6 or 7 can be tied directly to ground or V
DD
to program
a logic “0” or “1” state, respectively. See the following examples:
Figure 3. Trilevel Logic Example
CY25562
S0 = "M" (N/C)
S0
7
S1
S1 = "0" (GND)
V
DD
SSCC = "1"
5
SSCC = "1"
5
6
V
DD
SSCC = "1"
5
V
DD
V
DD
CY25562
S0 = "1"
S0
7
S1
CY25562
S0 = "1"
S0
7
S1
6
S1 = "0" (GND)
6
S1 = "1"
SSCG Theory of Operation
CY25562 is a PLL-type clock generator using a proprietary
Cypress design to modulate the reference clock. By precisely
controlling the bandwidth of the output clock, CY25562 becomes
a low-EMI clock generator. The theory and detailed operation of
CY25562 is discussed in the following sections.
EMI
All digital clocks generate unwanted energy in their harmonics.
Conventional digital clocks are square waves with a duty cycle
that is very close to 50 percent. Because of this 50/50 duty cycle,
digital clocks generate most of their harmonic energy in the odd
harmonics, that is; third, fifth, seventh, etc. The amount of energy
Document Number: 38-07392 Rev. *I
contained in the fundamental and odd harmonics can be reduced
by increasing the bandwidth of the fundamental clock frequency.
Conventional digital clocks have a very high Q factor; all the
energy at that frequency is concentrated in a very narrow
bandwidth, and consequently, higher energy peaks. Regulatory
agencies test electronic equipment by the amount of peak
energy radiated from the equipment. By reducing the peak
energy at the fundamental and harmonic frequencies, the
equipment under test satisfies agency requirements for EMI.
Conventional methods of reducing EMI use shielding, filtering,
multi-layer PCBs, etc. CY25562 reduces the peak energy in the
clock by increasing the clock bandwidth, thus lowering the Q.
Page 4 of 13
CY25562
SSCG
SSCG uses a patented technology of modulating the clock over
a very narrow bandwidth and controlled rate of change, both
peak and cycle-to-cycle. CY25562 takes a narrow band digital
reference clock in the range of 50 to 200 MHz and produces a
clock that sweeps between a controlled start (F1) and stop (F2)
frequency at a precise rate of change. To understand what
happens to a clock when SSCG is applied, consider a 200 MHz
clock with a 50 percent duty cycle, as shown in this figure.
important factor in the amount of EMI reduction realized from an
SSCG clock.
The modulation domain analyzer is used to visualize the sweep
waveform and sweep period.
Figure 4
shows the modulation
profile of a 200 MHz SSCG clock. Notice that the actual sweep
waveform is not a simple sine or sawtooth waveform.
Figure 4
also shows a scan of the same SSCG clock using a spectrum
analyzer. The spectrum analyzer scan shows a 10 dB reduction
in the peak RF energy when using CY25562 SSCG clock.
Modulation Rate
Spread spectrum clock generators use frequency modulation
(FM) to distribute energy over a specific band of frequencies. The
maximum frequency of the clock (Fmax) and minimum
frequency of the clock (Fmin) determine this band of frequencies.
The time required to transition from Fmin to Fmax and back to
Fmin is the period of the modulation rate, Tmod. Modulation
rates of SSCG clocks are generally referred to in terms of
frequency or Fmod = 1/Tmod.
The input clock frequency, Fin, and the internal divider count,
Cdiv, determine the modulation rate. In some SSCG clock gener-
ators, the selected range determines the internal divider count.
In other SSCG clocks, the internal divider count is fixed over the
operating range of the part. CY25562 has a fixed divider count
of 2332.
50 %
50 %
Tc = 5.0 ns
Clock frequency = fc = 200 MHz
Clock period = Tc = 1/200 MHz
If this clock is applied to the X
IN
/CLK pin of CY25562, the output
clock at pin 4 (SSCLK) sweeps back and forth between two
frequencies. These two frequencies, F1 and F2, calculate total
amount of spread or bandwidth applied to the reference clock at
pin 1. As the clock is making the transition, sweep, from F1 to
F2, the amount of time and sweep waveform become a very
Figure 4. SSCG Clock, Part Number, Fin = 200 MHz
Device
CY25562
Cdiv
2332
(All Ranges)
Example:
Device =
CY25562
Fin
=
200 MHz
Range =
S1 = 1, S0 = 1
Then;
Modulation Rate = Fmod = 200 MHz/2332 = 85.7 kHz.
Modulation Profile
Spectrum Analyzer
Document Number: 38-07392 Rev. *I
Page 5 of 13
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