MM74C373 • MM74C374 3-STATE Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop
October 1987
Revised January 2004
MM74C373 • MM74C374
3-STATE Octal D-Type Latch •
3-STATE Octal D-Type Flip-Flop
General Description
The MM74C373 and MM74C374 are integrated, comple-
mentary MOS (CMOS), 8-bit storage elements with 3-
STATE outputs. These outputs have been specially
designed to drive high capacitive loads, such as one might
find when driving a bus, and to have a fan out of 1 when
driving standard TTL. When a high logic level is applied to
the OUTPUT DISABLE input, all outputs go to a high
impedance state, regardless of what signals are present at
the other inputs and the state of the storage elements.
The MM74C373 is an 8-bit latch. When LATCH ENABLE is
high, the Q outputs will follow the D inputs. When LATCH
ENABLE goes low, data at the D inputs, which meets the
set-up and hold time requirements, will be retained at the
outputs until LATCH ENABLE returns high again.
The MM74C374 is an 8-bit, D-type, positive-edge triggered
flip-flop. Data at the D inputs, meeting the set-up and hold
time requirements, is transferred to the Q outputs on posi-
tive-going transitions of the CLOCK input.
Both the MM74C373 and the MM74C374 are being assem-
bled in 20-pin dual-in-line packages with 0.300” pin cen-
ters.
Features
s
Wide supply voltage range:
s
Low power consumption
s
TTL compatibility:
Fan out of 1driving standard TTL
s
Bus driving capability
s
3-STATE outputs
s
Eight storage elements in one package
s
Single CLOCK/LATCH ENABLE and OUTPUT DIS-
ABLE control inputs
s
20-pin dual-in-line package with 0.300” centers takes
half the board space of a 24-pin package
3V to 15V
s
High noise immunity: 0.45 V
CC
(typ.)
Ordering Code:
Order Number
MM74C373M
(Note 1)
MM74C373N
MM74C374N
Package Number
M20B
N20A
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Note 1:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2004 Fairchild Semiconductor Corporation
DS005906
www.fairchildsemi.com
MM74C373 • MM74C374
Absolute Maximum Ratings
(Note 2)
Voltage at Any Pin
Operating Temperature Range (T
A
)
MM74C373
Storage Temperature Range (T
S
)
Power Dissipation
Dual-In-Line
Small Outline
Operating V
CC
Range
Absolute Maximum V
CC
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260
°
C
700 mW
500 mW
3V to 15V
18V
Note 2:
“Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Tempera-
ture Range” they are not meant to imply that the devices should be oper-
ated at these limits. The table of “Electrical Characteristics” provides
conditions for actual device operation.
−
0.3V to V
CC
+
0.3V
−
55
°
C to
+
125
°
C
−
65
°
C to
+
150
°
C
DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise noted
Symbol
Parameter
Conditions
CMOS TO CMOS
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
I
IN(1)
I
IN(0)
I
OZ
I
CC
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
I
SOURCE
I
SOURCE
I
SINK
I
SINK
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Output Voltage
Logical “0” Output Voltage
Logical “1” Input Current
Logical “0” Input Current
3-STATE Leakage Current
Supply Current
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Output Voltage
Logical “0” Output Voltage
Output Source Current
Output Source Current
Output Sink Current
(N-Channel)
Output Sink Current
(N-Channel)
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V, I
O
= −10 µA
V
CC
=
10V, I
O
= −10 µA
V
CC
=
5V, I
O
=
10
µA
V
CC
=
10V, I
O
=
10
µA
V
CC
=
15V, V
IN
=
15V
V
CC
=
15V, V
IN
=
0V
V
CC
=
15V, V
O
=
15V
V
CC
=
15V, V
O
=
0V
V
CC
=
15V
V
CC
=
4.75V
V
CC
=
4.75V
V
CC
=
4.75V, I
O
= −360 µA
V
CC
=
4.75V, I
O
= −1.6
mA
V
CC
=
4.75V, I
O
=
1.6 mA
V
CC
=
5V, V
OUT
=
0V
T
A
=
25°C (Note 3)
V
CC
=
10V, V
OUT
=
0V
T
A
=
25°C (Note 3)
V
CC
=
5V, V
OUT
=
V
CC
T
A
=
25°C (Note 3)
V
CC
=
10V, V
OUT
=
V
CC
T
A
=
25°C (Note 3)
24
48
mA
6
12
mA
−24
−48
mA
−12
−24
OUTPUT DRIVE (Short Circuit Current)
mA
V
CC
−
0.4
2.4
0.4
V
CC
−
1.5
0.8
CMOS/LPTTL INTERFACE
V
V
V
V
−1.0
−1.0
0.005
−0.005
0.005
−0.005
0.05
300
1.0
4.5
9.0
0.5
1.0
1.0
3.5
8.0
1.5
2.0
V
V
V
V
µA
µA
µA
µA
Min
Typ
Max
Units
Note 3:
These are peak output current capabilities. Continuous output current is rated at 12 mA max.
www.fairchildsemi.com
4
MM74C373 • MM74C374
AC Electrical Characteristics
Symbol
t
pd0
, t
pd1
Parameter
Propagation Delay,
LATCH ENABLE to Output
(Note 4)
Conditions
Min
Typ
165
70
195
85
Max
330
140
390
170
ns
Units
MM74C373, T
A
=
25
°
C, C
L
=
50 pF, t
r
=
t
f
=
20 ns, unless otherwise noted
V
CC
=
5V, C
L
=
50 pF
V
CC
=
10V, C
L
=
50 pF
V
CC
=
5V, C
L
=
150 pF
V
CC
=
10V, C
L
=
150 pF
t
pd0
, t
pd1
Propagation Delay Data
In to Output
LATCH ENABLE
=
V
CC
V
CC
=
5V, C
L
=
50 pF
V
CC
=
10V, C
L
=
50 pF
V
CC
=
5V, C
L
=
150 pF
V
CC
=
10V, C
L
=
150 pF
t
SET-UP
Minimum Set-Up Time Data In
to CLOCK/LATCH ENABLE
t
HOLD
=
0 ns
V
CC
=
5V
V
CC
=
10V
f
MAX
Maximum LATCH ENABLE
Frequency
t
PWH
Minimum LATCH ENABLE
Pulse Width
t
r
, t
f
t
1H
, t
0H
Maximum LATCH ENABLE
Rise and Fall Time
Propagation Delay OUTPUT
DISABLE to High Impedance
State (from a Logic Level)
t
H1
, t
H0
Propagation Delay OUTPUT
DISABLE to Logic Level
(from High Impedance State)
t
THL
, t
TLH
Transition Time
V
CC
=
5V
V
CC
=
10V
V
CC
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
R
L
=
10k, C
L
=
5 pF
V
CC
=
5V
V
CC
=
10V
R
L
=
10k, C
L
=
50 pF
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V, C
L
=
50 pF
V
CC
=
10V, C
L
=
50 pF
V
CC
=
5V, C
L
=
150 pF
V
CC
=
10V, C
L
=
150 pF
C
LE
C
OD
C
IN
C
OUT
C
PD
Input Capacitance
Input Capacitance
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
LE Input (Note 5)
OUTPUT DISABLE
Input (Note 5)
Any Other Input (Note 5)
High Impedance
State (Note 5)
Per Package (Note 6)
200
pF
Note 4:
AC Parameters are guaranteed by DC correlated testing.
Note 5:
Capacitance is guaranteed by periodic testing.
Note 6:
C
PD
determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note
AN-90.
155
70
185
85
70
35
3.5
4.5
6.7
9.0
75
55
NA
NA
105
60
105
45
65
35
110
70
7.5
7.5
5
10
310
140
370
170
140
70
ns
ns
MHz
150
110
ns
µs
210
120
210
90
130
70
220
140
10
10
7.5
15
ns
ns
ns
pF
pF
pF
pF
5
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