IS61LV2568
256K x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
• High-speed access times: 10 and 12 ns
• High-performance, low-power CMOS process
• Multiple center power and ground pins for
greater noise immunity
• Easy memory expansion with
CE
and
OE
options
•
CE
power-down
• Low power: 540 mW @ 10 ns
36 mW standby mode
• TTL compatible inputs and outputs
• Single 3.3V ±10% power supply
• Packages available:
– 36-pin 400-mil SOJ
– 44-pin TSOP (Type II)
ISSI
®
FEBRUARY 2003
DESCRIPTION
The
ISSI
IS61LV2568 is a very high-speed, low power,
262,144-word by 8-bit CMOS static RAM. The IS61LV2568
is fabricated using
ISSI
's high-performance CMOS tech-
nology. This highly reliable process coupled with innova-
tive circuit design techniques, yields higher performance
and low power consumption devices.
When
CE
is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 36mW (max.) with CMOS input levels.
The IS61LV2568 operates from a single 3.3V power
supply and all inputs are TTL-compatible.
The IS61LV2568 is available in 36-pin 400-mil SOJ, and
44-pin TSOP (Type II) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A17
DECODER
256K X 8
MEMORY ARRAY
V
DD
GND
I/O
DATA
CIRCUIT
I/O0-I/O7
COLUMN I/O
CE
OE
WE
CONTROL
CIRCUIT
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
02/07/03
1
IS61LV2568
TRUTH TABLE
Mode
WE
X
H
H
L
CE
H
L
L
L
OE
X
H
L
X
I/O Operation
High-Z
High-Z
D
OUT
D
IN
V
DD
Current
I
SB
1
, I
SB
2
I
CC
I
CC
I
CC
Not Selected
(Power-down)
Output Disabled
Read
Write
ISSI
®
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
DD
V
TERM
T
STG
P
D
Parameter
Supply voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
Power Dissipation
Value
–0.5 to +4.6
–0.5 to V
DD
+ 0.5
–65 to +150
1.0
Unit
V
V
°C
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
V
DD
3.3V ± 10%
3.3V ± 10%
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
02/07/03
3
IS61LV2568
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol Parameter
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
(1)
Input LOW Voltage
(1)
Input Leakage
Output Leakage
GND
≤
V
IN
≤
V
DD
GND
≤
V
OUT
≤
V
DD
, Outputs Disabled
Com.
Ind.
Com.
Ind.
Test Conditions
V
DD
= Min., I
OH
= –4.0 mA
V
DD
= Min., I
OL
= 8.0 mA
Min.
2.4
—
2.0
–0.3
–1
–5
–1
–5
ISSI
Max.
—
0.4
V
DD
+ 0.3
0.8
1
5
1
5
®
Unit
V
V
V
V
µA
µA
Note:
1. V
IL
(min) = –0.3V (DC); V
IL
(min) = –2.0V (pulse width - 2.0 ns).
V
IH
(max) = V
DD
+ 0.3V (DC); V
IH
(max) = V
DD
+ 2.0V (pulse width - 2.0 ns).
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-10 ns
Symbol
I
CC
I
SB
1
Parameter
V
DD
Operating
Supply Current
TTL Standby
Current
(TTL Inputs)
CMOS Standby
Current
(CMOS Inputs)
Test Conditions
V
DD
= Max.,
CE
= V
IL
I
OUT
= 0 mA, f = Max.
V
DD
= Max.,
V
IN
= V
IH
or V
IL
CE
≥
V
IH
, f = max
V
DD
= Max.,
CE
≥
V
DD
– 0.2V,
V
IN
≥
V
DD
– 0.2V, or
V
IN
≤
0.2V, f = 0
Com.
Ind.
Com.
Ind.
Com.
Ind.
Min. Max.
—
—
—
—
—
—
125
135
40
50
10
20
-12 ns
Min. Max.
—
—
—
—
—
—
110
120
35
45
10
20
Unit
mA
mA
I
SB
2
mA
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE
(1,2)
Symbol
C
IN
C
I/O
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
6
8
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25°C, f = 1 MHz, V
DD
= 3.3V.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
02/07/03
IS61LV2568
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
ISSI
®
AC TEST LOADS
319
Ω
3.3V
319
Ω
3.3V
OUTPUT
30 pF
Including
jig and
scope
353
Ω
OUTPUT
5 pF
Including
jig and
scope
353
Ω
Figure 1
Figure 2
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
Symbol Parameter
-10 ns
Min.
Max.
10
—
3
—
—
0
0
3
0
—
10
—
10
4
—
4
—
4
-12 ns
Min. Max.
12
—
3
—
—
0
0
3
0
—
12
—
12
5
—
5
—
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
(2)
t
HZOE
(2)
t
LZCE
(2)
t
HZCE
(2)
Read Cycle Time
Address Access Time
Output Hold Time
CE
Access Time
OE
Access Time
OE
to Low-Z Output
OE
to High-Z Output
CE
to Low-Z Output
CE
to High-Z Output
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V,
input pulse levels of 0 to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage.
Not 100% tested.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
02/07/03
5
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