IS61LF25632T/D/J
IS61LF25636T/D/J IS61LF51218T/D/J
256K x 32, 256K x 36, 512K x 18
SYNCHRONOUS FLOW-THROUGH
STATIC RAM
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global
Write
• Clock controlled, registered address, data
and control
• Interleaved or linear burst sequence control
using MODE input
• Three chip enable option for simple depth
expansion and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP and
119-pin PBGA package
• Power Supply
+ 3.3V V
DD
+ 3.3V or 2.5V V
DDQ
(I/0)
• Snooze MODE for reduced-power standby
• T version (three chip selects)
• J version (PBGA Package with JTAG)
• D version (two chip selects)
• JTAG Boundary Scan for PBGA.
ISSI
OCTOBER 2002
®
DESCRIPTION
The
ISSI
IS61LF25632, IS61LF25636, and IS61LF51218 are
high-speed, low-power synchronous static RAMs designed to
provide a burstable, high-performance and memories for
commucation and networking applications. The IS61LF25632
is organized as 262,144 words by 32 bits and the IS61LF25636
is organized as 262,144 words by 36 bits. The IS61LF51218 is
organized as 524,288 words by 18 bits. Fabricated with
ISSI
's
advanced CMOS technology, the device integrates a 2-bit
burst counter, high-speed SRAM core, and high-drive capability
outputs into a single monolithic circuit. All synchronous inputs
pass through registers that are controlled by a positive-edge-
triggered single clock input.
Write cycles are internally self-timed and are initiated by the rising
edge of the clock input. Write cycles can be from one to four bytes
wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written. Byte
write operation is performed by using byte write enable
(BWE).input combined with one or more individual byte write
signals (BWx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the byte write
controls.
Bursts can be initiated with either
ADSP
(Address Status
Processor) or
ADSC
(Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated internally
and controlled by the
ADV
(burst address advance) input pin.
The mode pin is used to select the burst sequence order, Linear
burst is achieved when this pin is tied LOW. Interleave burst is
achieved when this pin is tied HIGH or left floating.
FAST ACCESS TIME
Symbol
t
KQ
t
KC
Parameter
Clock Access Time
Cycle Time
Frequency
6.5
6.5
7.5
133
7.5
7.5
8.5
117
Units
ns
ns
MHz
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
10/06/02
1
IS61LF25632T/D/J
IS61LF25636T/D/J
PIN CONFIGURATION
IS61LF51218T/D/J
ISSI
100-Pin TQFP (D Version)
A
A
CE
CE2
BWd
BWc
BWb
BWa
A
V
DD
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
®
119-pin PBGA (Top View) (D Version)
1
A
V
DDQ
B
NC
C
NC
D
DQc
E
DQc
F
V
DDQ
G
DQc
H
DQc
J
V
DDQ
K
DQd
L
DQd
M
V
DDQ
N
DQd
P
DQd
R
NC
T
NC
U
V
DDQ
2
3
4
5
6
7
A
CE2
A
NC
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
NC
A
NC
NC
A
A
A
GND
GND
GND
BWc
GND
NC
GND
BWd
GND
GND
GND
MODE
A
NC
ADSP
ADSC
V
DD
NC
CE
OE
ADV
GW
V
DD
CLK
NC
BWE
A1
A0
V
DD
A
NC
A
A
A
GND
GND
GND
BWb
GND
NC
GND
BWa
GND
GND
GND
GND
A
NC
A
A
A
NC
DQb
DQb
DQb
DQb
V
DD
DQa
DQa
DQa
DQa
NC
A
NC
NC
V
DDQ
NC
NC
DQb
DQb
V
DDQ
DQb
DQb
V
DDQ
DQa
DQa
V
DDQ
DQa
DQa
NC
ZZ
V
DDQ
NC
DQc
DQc
V
DDQ
GND
DQc
DQc
DQc
DQc
GND
V
DDQ
DQc
DQc
NC
V
DD
NC
GND
DQd
DQd
V
DDQ
GND
DQd
DQd
DQd
DQd
GND
V
DDQ
DQd
DQd
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE
A
A
A
A
A1
A0
NC
NC
GND
V
DD
NC
NC
A
A
A
A
A
A
A
NC
DQb
DQb
V
DDQ
GND
DQb
DQb
DQb
DQb
GND
V
DDQ
DQb
DQb
GND
NC
V
DD
ZZ
DQa
DQa
V
DDQ
GND
DQa
DQa
DQa
DQa
GND
V
DDQ
DQa
DQa
NC
256K x 32
256K x 32
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
ZZ
GW
CE,
CE2
OE
DQa-DQd
MODE
V
DD
GND
V
DDQ
Synchronous Global Write Enable
Synchronous Chip Enable
Output Enable
Synchronous Data Input/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
Isolated Output Buffer Supply:
+3.3V or 2.5V
Snooze Enable
A
CLK
ADSP
ADSC
ADV
BWa-BWd
BWE
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev.A
10/06/02
3
IS61LF25632T/D/J
IS61LF25636T/D/J
PIN CONFIGURATION
100-Pin TQFP (T Version)
IS61LF51218T/D/J
ISSI
®
NC
DQc
DQc
V
DDQ
GND
DQc
DQc
DQc
DQc
GND
V
DDQ
DQc
DQc
NC
V
DD
NC
GND
DQd
DQd
V
DDQ
GND
DQd
DQd
DQd
DQd
GND
V
DDQ
DQd
DQd
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
A
CE
CE2
BWd
BWc
BWb
BWa
CE2
V
DD
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
NC
DQb
DQb
V
DDQ
GND
DQb
DQb
DQb
DQb
GND
V
DDQ
DQb
DQb
GND
NC
V
DD
ZZ
DQa
DQa
V
DDQ
GND
DQa
DQa
DQa
DQa
GND
V
DDQ
DQa
DQa
NC
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
ZZ
GW
OE
DQa-DQd
MODE
V
DD
GND
V
DDQ
Synchronous Global Write Enable
Output Enable
Synchronous Data Input/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
Isolated Output Buffer Supply:
+3.3V or 2.5V
Snooze Enable
CE, CE2,
CE2 Synchronous Chip Enable
A
CLK
ADSP
ADSC
ADV
BWa-BWd
BWE
4
MODE
A
A
A
A
A1
A0
NC
NC
GND
V
DD
NC
A
A
A
A
A
A
A
A
256K x 32
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
10/06/02
IS61LF25632T/D/J
IS61LF25636T/D/J
PIN CONFIGURATION
100-pin TQFP (T Version)
IS61LF51218T/D/J
ISSI
100-Pin TQFP (D Version)
A
A
CE
CE2
BWd
BWc
BWb
BWa
A
V
DD
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
®
A
A
CE
CE2
BWd
BWc
BWb
BWa
CE2
V
DD
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
DQPc
DQc
DQc
V
DDQ
GND
DQc
DQc
DQc
DQc
GND
V
DDQ
DQc
DQc
NC
V
DD
NC
GND
DQd
DQd
V
DDQ
GND
DQd
DQd
DQd
DQd
GND
V
DDQ
DQd
DQd
DQPd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DQPb
DQb
DQb
V
DDQ
GND
DQb
DQb
DQb
DQb
GND
V
DDQ
DQb
DQb
GND
NC
V
DD
ZZ
DQa
DQa
V
DDQ
GND
DQa
DQa
DQa
DQa
GND
V
DDQ
DQa
DQa
DQPa
DQPc
DQc
DQc
V
DDQ
GND
DQc
DQc
DQc
DQc
GND
V
DDQ
DQc
DQc
NC
V
DD
NC
GND
DQd
DQd
V
DDQ
GND
DQd
DQd
DQd
DQd
GND
V
DDQ
DQd
DQd
DQPd
MODE
A
A
A
A
A1
A0
NC
NC
GND
V
DD
NC
A
A
A
A
A
A
A
A
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DQPb
DQb
DQb
V
DDQ
GND
DQb
DQb
DQb
DQb
GND
V
DDQ
DQb
DQb
GND
NC
V
DD
ZZ
DQa
DQa
V
DDQ
GND
DQa
DQa
DQa
DQa
GND
V
DDQ
DQa
DQa
DQPa
256K x 36
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Individual Byte Write Enable
Synchronous Byte Write Enable
TMS, TDI
TCK, TDO
GW
CE,
CE2
OE
DQa-DQd
MODE
V
DD
GND
V
DDQ
ZZ
DQPa-DQPd
A
CLK
ADSP
ADSC
ADV
BWa-BWd
BWE
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev.A
10/06/02
MODE
A
A
A
A
A1
A0
NC
NC
GND
V
DD
NC
NC
A
A
A
A
A
A
A
256K x 36
JTAG Boundry Scan Pins
Synchronous Global Write Enable
Synchronous Chip Enable
Output Enable
Synchronous Data Input/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
Isolated Output Buffer Supply:
+3.3V or 2.5V
Snooze Enable
Parity Data I/O
5
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