Hitachi Single-Chip Microcomputer
H8S/2238 Series
H8S/2238B
HD6432238B, HD6432238BW
H8S/2238R
HD6432238R
H8S/2236B
HD6432236B, HD6432236BW
H8S/2236R
HD6432236R
H8S/2238F-ZTAT™
HD64F2238B, HD64F2238R
Hardware Manual
ADE-602-176B
Rev. 3.0
3/18/02
Hitachi Ltd.
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s
patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party’s
rights, including intellectual property rights, in connection with use of the information
contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi
semiconductor products.
Preface
The H8S/2238 Series is a series of high-performance microcontrollers with a 32-bit H8S/2000
CPU core, and a set of on-chip supporting functions required for system configuration.
The H8S/2000 CPU can execute basic instructions in one state, and is provided with sixteen 16-bit
general registers with a 32-bit internal configuration, and a concise and optimized instruction set.
The CPU can handle a 16-Mbyte linear address space (architecturally 4 Gbytes). Programs based
on the high-level language C can also be run efficiently.
The address space is divided into eight areas. The data bus width and access states can be selected
for each of these areas, and various kinds of memory can be connected fast and easily.
Single-power-supply flash memory (F-ZTAT™*) and mask ROM versions are available,
providing a quick and flexible response to conditions from ramp-up through full-scale volume
production, even for applications with frequently changing specifications.
On-chip supporting functions include a 16-bit timer pulse unit (TPU), 8-bit timer unit (TMR),
watchdog timer (WDT), serial communication interface (SCI), I
2
C bus interface (IIC), A/D
converter, D/A converter, and I/O ports.
In addition, an on-chip data transfer controller (DTC) is provided, enabling high-speed data
transfer without CPU intervention.
Use of the H8S/2238 Series enables compact, high-performance systems to be implemented easily.
This manual describes the hardware of the H8S/2238 Series. Refer to the
H8S/2600 Series and
H8S/2000 Series Programming Manual
for a detailed description of the instruction set.
Note: * F-ZTAT is a trademark of Hitachi, Ltd.
Main Revisions and Additions in this Edition
Page
All
Item
Revisions (See Manual for Details)
112-pin plastic TFBGA (BP-112) is added to package
types.
Product code of HD64F2238M is amended to
HD64F2238B.
HD6432238RW and HD6432236RW (mask ROM
version) added
9
66
120
203
402
494
523
524
531
545
546
1.3 Pin Description
2.10 Usage Notes
6.2.3 Break Control Register A
(BCRA)
8.5 Usage Notes
12.2.2 Timer Control/Status
Register (TCSR)
14.2.3 Serial Mode Register
(SMR)
15.2.1 I
2
C Bus Data Register
(ICDR)
15.2.5 I
2
C Bus Control Register
(ICCR)
15.3.2 Master Transmit
Operation
Figure 1-4 Pin Arrangement added
Description of STM/LDM instruction added
Note on condition match flag A added
Description of module stop amended
Note on overflow flag added
Values set to bits 6, 3, and 2 amended
Description amended
Second setting condition of TDRE deleted
Description of setting conditions 1 and 2 of bit 4 partly
deleted
Operation entirely amended
Figure 15-6 Master Transmit Mode Operation Timing
Example
Entirely amended
548
15.3.3 Master Receive
Operation
Figure 15-7 Example of Master Transmit Mode
Continuous Transmit Operation Timing
Deleted
546, 547 15.3.3 Master Receive
Operation
548
Operation entirely amended
Figure 15-8 Example of Master Receive Mode
Operation Timing is divided into two figures (figures
15-7 and 15-8) and entirely amended
Figure 15-14 Flowchart for Master Transmit Mode and
figure 15-15 Flowchart for Master Receive Mode
Entirely amended
559
15.3.10 Initialization of Internal
State
Description of procedure when initializing IIC state
amended
556, 557 15.3.9 Sample Flowcharts
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
