High Reliability Serial EEPROMs
I C BUS
BR24□□□□family
BR24T□□□□Series
●Description
2
BR24T□□□-W series is a serial EEPROM of I C BUS interface method
No.11001EAT21
2
●Features
2
1) Completely conforming to the world standard I C BUS.
All controls available by 2 ports of serial clock (SCL) and serial data(SDA)
2) Other devices than EEPROM can be connected to the same port, saving microcontroller port
3) 1.7V½5.5V single power source action most suitable for battery use
4) 1.7V½5.5Vwide limit of action voltage, possible FAST MODE 400KHz action
5) Page write mode useful for initial value write at factory shipment
6) Auto erase and auto end function at data write
7) Low current consumption
8) Write mistake prevention function
Write (write protect) function added
Write mistake prevention function at low voltage
9) DIP-T8/SOP8/SOP-J8/SSOP-B8/TSSOP-B8/TSSOP-B8J/MSOP8/VSON008X2030 various packages
10) Data rewrite up to 1,000,000 times
11) Data kept for 40 years
12) Noise filter built in SCL / SDA terminal
13) Shipment data all address FFh
●BR24T
series
Capacity Bit format
1Kbit
2Kbit
4Kbit
8Kbit
16Kbit
32Kbit
64Kbit
128Kbit
256Kbit
512Kbit
128×8
256×8
512×8
1K×8
2K×8
4K×8
8K×8
16K×8
32K×8
64K×8
Type
Power source
Voltage
DIP-T8
SOP8
SOP-J8
SSOP-B8 TSSOP-B8 TSSOP-B8J
MSOP8
VSON008
X2030
BR24T01-W 1.7½5.5V
BR24T02-W 1.7½5.5V
BR24T04-W 1.7½5.5V
BR24T08-W 1.7½5.5V
BR24T16-W 1.7½5.5V
BR24T32-W 1.7½5.5V
BR24T64-W 1.7½5.5V
BR24T128-W 1.7½5.5V
BR24T256-W 1.7½5.5V
BR24T512-W 1.7½5.5V
BR24T1M-W 1.7½5.5V
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1024Kbit 128K×8
☆:Developing
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© 2011 ROHM Co., Ltd. All rights reserved.
1/21
2011.03 - Rev.A
BR24T□□□□Series
●Absolute
maximum ratings
(Ta=25℃)
Parameter
Impressed voltage
Symbol
V
CC
Ratings
-0.3½+6.5
450 (SOP8)
*1
Technical Note
●Memory
cell characteristics
(Ta=25℃, Vcc=1.7½
5.5V)
Limits
Parameter
Unit
Min.
Typ.
Max
Number of data
rewrite times
*1
Data hold years
*1
*1Not 100% TESTED
Unit
V
1,000,000
40
－
－
－
－
Times
Years
450 (SOP-J8)
*2
300 (SSOP-B8)
Permissible
dissipation
Pd
*3
330 (TSSOP-B8)
*4
310 (TSSOP-B8J)
*5
310 (MSOP8)
*6
300 (VSON008X2030)
*7
800 (DIP-T8)
*8
mW
●Recommended
operating conditions
℃
℃
Parameter
Power source
voltage
Input voltage
Symbol
Vcc
V
IN
Ratings
1.7½5.5
V
0½Vcc
Unit
Storage
temperature range
Action
temperature range
Terminal voltage
Junction
temperature
*10
*1,*2
*3,*7
*4
*5, *6
*8
*9
Tstg
Topr
‐
Tjmax
－65½+150
－40½+85
-0.3½Vcc+1.0
150
*9
V
℃
*10
When using at Ta=25℃ or higher 4.5mW to be reduced per 1℃.
When using at Ta=25℃ or higher 3.0mW to be reduced per 1℃.
When using at Ta=25℃ or higher 3.3mW to be reduced per 1℃.
When using at Ta=25℃ or higher 3.1mW to be reduced per 1℃.
When using at Ta=25℃ or higher 8.1mW to be reduced per 1℃.
The Max value of Terminal Voltage is not over 6.5V.
When the pulse width is 50ns or less, the Min value of
Terminal Voltage is not under -1.0V. (BR24T16/32/64/128/256/512/1M-W)
the Min value of Terminal Voltage is not under -0.8V. (BR24T01/02/04/08-W)
Junction temperature at the storage condition.
●Electrical
characteristics
(Unless otherwise specified, Ta=－40½+85℃, VCC=1.7½5.5V)
Limits
Parameter
Symbol
Unit
Min.
Typ.
Max.
“H” input voltage 1
“L” input voltage 1
“L” output voltage 1
“L” output voltage 2
Input leak current
Output leak current
V
IH1
V
IL1
V
OL1
V
OL2
I
LI
I
LO
0.7Vcc
-0.3
－
－
－1
－1
－
－
－
－
I
CC2
－
－
Standby current
I
SB
－
－
3.0
－
－
2.0
2.0
µA
*2
Conditions
－
－
－
－
－
－
－
－
－
－
Vcc+1.0
0.3Vcc
0.4
0.2
1
1
2.0
2.5
4.5
0.5
V
V
V
V
µA
µA
I
OL
=3.0mA, 2.5V≦Vcc≦5.5V (SDA)
I
OL
=0.7mA, 1.7V≦Vcc＜2.5V (SDA)
V
IN
=0½Vcc
V
OUT
=0½Vcc (SDA)
Vcc=5.5V,f
SCL
=400kHz, t
WR
=5ms,
Byte write, Page write
BR24T01/02/04/08/16/32/64-W
Vcc=5.5V,f
SCL
=400kHz, t
WR
=5ms,
Byte write, Page write
BR24T128/256-W
Vcc=5.5V,f
SCL
=400kHz, t
WR
=5ms,
Byte write, Page write
BR24T512/1M-W
Vcc=5.5V,f
SCL
=400kHz
Random read, current read, sequential read
BR24T01/02/04/08/16/32/64/128/256-W
Vcc=5.5V,f
SCL
=400kHz
Random read, current read, sequential read
BR24T512/1M-W
Vcc=5.5V, SDA・SCL=Vcc
A0,A1,A2=GND,WP=GND
BR24T01/02/04/08/16/32/64/128/256-W
Vcc=5.5V, SDA・SCL=Vcc
A0, A1, A2=GND, WP=GND
BR24T512/1M-W
I
CC1
Current consumption
at action
mA
mA
○
Radiation resistance design is not made.
*1 BR24T512/1M-W is a target value because it is developing.
*2 When the pulse width is 50ns or less, it is -1.0V. (BR24T16/32/64/128/256/512/1M-W)
When the pulse width is 50ns or less, it is -0.8V. (BR24T01/02/04/08-W)
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© 2011 ROHM Co., Ltd. All rights reserved.
2/21
2011.03 - Rev.A
BR24T□□□□Series
●Action
timing characteristics
(Unless otherwise specified, Ta=－40½+85℃, VCC=1.7½5.5V)
Limits
Parameter
Symbol
Min.
Typ.
Max.
SCL frequency
Data clock “HIGH“ time
Data clock “LOW“ time
SDA, SCL rise time
SDA, SCL fall time
*1
*1
Technical Note
Unit
kHz
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
ms
µs
µs
µs
µs
fSCL
tHIGH
tLOW
tR
tF
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tPD
tDH
tSU:STO
tBUF
tWR
tI
tHD:WP
tSU:WP
tHIGH:WP
－
0.6
1.2
－
－
0.6
0.6
0
100
0.1
0.1
0.6
1.2
－
－
1.0
0.1
1.0
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
400
－
－
1.0
1.0
－
－
－
－
0.9
－
－
－
5
0.1
－
－
－
Start condition hold time
Start condition setup time
Input data hold time
Input data setup time
Output data delay time
Output data hold time
Stop condition setup time
Bus release time before transfer start
Internal write cycle time
Noise removal valid period (SDA, SCL terminal)
WP hold time
WP setup time
WP valid time
*1 Not 100% TESTED.
Condition Input data level:VIL=0.2×Vcc VIH=0.8×Vcc
Input data timing refarence level: 0.3×Vcc/0.7×Vcc
Output data timing refarence level: 0.3×Vcc/0.7×Vcc
Rise/Fall time :
≦20ns
●Sync
data input / output timing
tR
SCL
30%
70% 70%
30%
tF
tHIGH
70%
30%
70%
30%
70%
tLOW
tSU:DAT
70%
70%
70%
tHD:DAT
DATA(1)
D1
D0
ACK
DATA(n)
ACK
70%
70%
30%
SDA
(input)
SDA
(output)
tWR
30%
30%
tBUF
tPD
tDH
70%
30%
70%
30%
○
Input read at the rise edge of SCL
○
Data output in sync with the fall of SCL
tSU:WP
tHD:WP
STOP CONDITION
Fig.1-(a) Sync data input / output timing
Fig.1-(d) WP timing at write execution
70%
70%
70%
DATA(1)
D1
D0
ACK
DATA(n)
ACK
tHIGH:WP
70%
tSU:STA
70%
30%
tHD:STA
tSU:STO
tWR
70%
30%
70%
START CONDITION
STOP CONDITION
Fig.1-(b) Start-stop bit timing
Fig.1-(e) WP timing at write cancel
D0
write data
(n-th address)
ACK
70%
70%
tWR
STOP CONDITION
START CONDITION
Fig.1-(c) Write cycle timing
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© 2011 ROHM Co., Ltd. All rights reserved.
3/21
2011.03 - Rev.A
BR24T□□□□Series
●Block
diagram
*2
Technical Note
A0
1
*1
1Kbit½1024Kbit EEPROM array
8bit
*1
7bit
8bit
9bit
10bit
11bit
12bit
8
Vcc
A0
1
A1
13bit
14bit
15bit
16bit
17bit
2
*2
A1
2
Address
decoder
Word
address register
Data
register
7
WP
A2
3
START
*2
STOP
A2
3
Control circuit
ACK
6
SCL
GND
4
BR24T01-W
BR24T02-W
BR24T04-W
BR24T08-W
BR24T16-W
BR24T32-W
BR24T64-W
BR24T128-W
BR24T256-W
BR24T512-W
BR24T1M-W
8
Vcc
7
WP
6
SCL
5
SDA
GND
4
High voltage
generating circuit
Power source
voltage detection
5
SDA
*
1
7bit: BR24T01-W
8bit: BR24T02-W
9bit: BR24T04-W
10bit: BR24T08-W
11bit: BR24T16-W
12bit: BR24T32-W
13bit: BR24T64-W
14bit: BR24T128-W
15bit: BR24T256-W
16bit: BR24T512-W
17bit: BR24T1M-W
*2
A0= Don't use : BR24T04-W, BR24T1M-W
A0, A1=Don't use: BR24T08-W
A0, A1, A2=Don't use: BR24T16-W
Fig.2 Block diagram
●Pin
assignment and description
Terminal Input/
BR24T01-W
Name
Output
A0
A1
A2
GND
SDA
SCL
WP
Vcc
Input
Input
Input
－
Input/
output
Input
Input
－
BR24T02-W
BR24T04-W
BR24T08-W
BR24T16-W
BR24T32/64/
128/256/512-W
BR24T1M-W
Slave address setting
Slave address setting
Slave address setting
Don’t use*
Don’t use*
Don’t use*
Slave address
Don’t use*
setting
Slave address setting
Slave address setting
Reference voltage of all input / output, 0V
Serial data input serial data output
Serial clock input
Write protect terminal
Connect the power source.
*Pins not used as device address may be set to any of ‘H’, 'L', and 'Hi-Z'.
●Characteristic
data (The following values are Typ. ones.)
6
5
H INPUT VOLTAGE : V
IH1
(V)
4
3
2
1
0
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
6
6
1
L OUTPUT VOLTAGE : V
OL1
(V)
L INPUT VOLTAGE : V
IL1
(V)
Ta=-40℃
Ta=25℃
Ta=85℃
5
4
3
2
1
0
0
Ta=-40℃
Ta=25℃
Ta=85℃
0.8
0.6
0.4
0.2
0
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
SPEC
SPEC
1
2
3
4
5
6
0
1
SUPPLY VOLTAGE : Vcc(V)
2
3
4
5
L OUTPUT CURRENT : I
OL
(mA)
6
Fig.3 'H' input voltage V
IH1
(A0,A1,A2,SCL,SDA,WP)
1
L OUTPUT VOLTAGE : V
OL2
(V)
0.8
0.6
1.2
Fig.4 'L' input voltage V
IL1
(A0,A1,A2,SCL,SDA,WP)
1.2
OUTPUT LEAK CURRENT : I
LO
(uA)
Fig.5 'L' output voltage V
OL1
-I
OL
(Vcc=1.7V)
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
0.4
0.2
0
0
1
2
3
4
5
6
L OUTPUT CURRENT : I
OL
(mA)
INPUT LEAK CURRENT : I
LI
(uA)
1
0.8
0.6
0.4
0.2
0
0
1
2
3
4
5
6
SUPPLYVOLTAGE : Vcc(V)
SPEC
1
0.8
0.6
0.4
0.2
0
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
6
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
Fig.6 'L' output voltage V
OL2
-I
OL
(Vcc=2.5V)
Fig.7 Input leak current I
LI
(A0,A1,A2,SCL,WP)
Fig.8 Output leak current I
LO
(SDA)
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© 2011 ROHM Co., Ltd. All rights reserved.
4/21
2011.03 - Rev.A
BR24T□□□□Series
●Characteristic
data (The following values are Typ. ones.)
2.5
Technical Note
3.5
6
SPEC
CURRENT CONSUMPTION
AT WRITING : Icc1(mA)
2
3
CURRENT CONSUMPTION
AT WRITING : Icc1(mA)
CURRENT CONSUMPTION
AT WRITING : Icc1(mA)
2.5
2
1.5
1
0.5
0
0
1
2
3
4
5
6
SPEC
5
4
3
2
1
0
0
1
2
3
4
5
6
1.5
1
0.5
0
0
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
The plan for
inserting data.
(BR24T512/1M-W)
1
2
3
4
5
6
SUPPLY VOLTAGE : Vcc(V)
SUPPLY VOLTAGE : Vcc(V)
SUPPLY VOLTAGE : Vcc(V)
Fig.9 Current consumption at WRITE operation I
CC
1
(fscl=400kHz BR24T01/02/04/08/16/32/64-W)
0.6
Fig.10 Current consumption at WRITE operation Icc1
(fscl=400kHz BR24T128/256-W)
0.6
Fig.11 Current consumption at WRITE operation Icc1
(fscl=400kHz BR24T512/1M-W)
2.5
STANBY CURRENT : I
SB
(uA)
SPEC
CURRENT CONSUMPTION
AT READING : Icc2(mA)
0.5
0.4
0.3
0.2
0.1
0
0
1
2
3
4
5
6
0
0
SUPPLY VOLTAGE : Vcc(V)
1
2
3
4
5
6
SUPPLY VOLTAGE : Vcc(V)
CURRENT CONSUMPTION
AT READING : Icc2(mA)
0.5
0.4
0.3
0.2
0.1
Ta=-40℃
Ta=25℃
Ta=85℃
The plan for
inserting data.
(BR24T512/1M-W)
2
1.5
1
0.5
0
0
1
2
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
3
4
5
6
SUPPLY VOLTAGE : Vcc(V)
Fig.12 Current consumption at READ operation I
CC
2
(fscl=400kHz BR24T01/02/04/08/16/32/64/128/256-W)
2.5
STANBY CURRENT : I
SB
(uA)
SCL FREQUENCY : f½½½（½H
Z
）
2
1.5
1
0.5
0
0
1
2
3
4
5
6
Fig.13 Current consumption at READ operation I
CC
2
(fscl=400kHz BR24T512/1M-W)
10000
Fig.14 Stanby operation I
SB
(fscl=400kHz BR24T01/02/04/08/16/32/64/128/256-W)
1
DATA CLK H TIME : t
HIGH
(us)
0.8
The plan for
inserting data.
(BR24T512/1M-W)
1000
SPEC
100
10
1
0.1
0
1
2
3
4
5
6
SUPPLY VOLTAGE : Vcc(V)
SPEC
0.6
0.4
0.2
0
0
1
2
3
4
5
6
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
SUPPLY VOLTAGE : Vcc(V)
SUPPLY VOLTAGE : Vcc(V)
Fig.15 Stanby operation I
SB
(fscl=400kHz BR24T512/1M-W)
START CONDITION HOLD TIME : t
HD : STA
(us)
Fig.16 SCL frequency f
SCL
1
0.8
Fig.17 Data clock High Period t
HIGH
1.1
START CONDITION
SET UP TIME : tSU:STA(us)
0.9
0.7
0.5
0.3
0.1
-0.1
1.5
ＤＡＴＡ CLK L TIME : t
LOW
(us)
SPEC
1.2
0.9
0.6
0.3
0
0
1
2
3
4
5
6
SPEC
0.6
0.4
0.2
0
0
1
2
3
4
5
6
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
0
1
2
3
4
5
6
SUPPLY VOLTAGE : Vcc（V）
SUPPLY VOLTAGE : Vcc(V)
SUPPLY VOLTAGE : Vcc(V)
Fig.18 Data clock Low Period t
LOW
Fig.19 Start Condition Hold Time t
HD : STA
Fig.20 Start Condition Setup Time t
SU : STA
INPUT DATA HOLD TIME : t
HD :DAT
(ns)
SPEC
0
-50
-100
-150
-200
0
1
2
3
4
5
6
SPEC
0
-50
INPUT DATA SET UP TIME : t
SU: DAT
(ns)
INPUT DATA HOLD TIME : t
HD: STA
(ns)
50
50
300
200
SPEC
100
0
-100
-200
0
1
2
3
4
5
6
Ta=-40℃
Ta=25℃
Ta=85℃
-100
-150
-200
0
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
1
2
3
4
5
6
SUPPLY VOLTAGE : Vcc(V)
SUPPLY VOLTAGE : Vcc(V)
SUPPLY VOLTAGE : Vcc(V)
Fig.21 Input Data Hold Time t
HD : DAT
（HIGH）
Fig.22 Input Data Hold Time
½
HD : DAT
(LOW）
Fig.23 Input Data Setup Time
½
SU: DAT
(HIGH)
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2011.03 - Rev.A
DSP 与 ARM 处理器
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