SDC-630/632/634* A/ST
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®
10-, 12-, OR 14-BIT SYNCHRO-TO-DIGITAL/
RESOLVER-TO-DIGITAL CONVERTER
FEATURES
•
Low Cost Pin-for-Pin Replacement for
SDC-630/632/634 Series. For all New
Designs.
•
Industry Standard Low Profile Modular
Converters
•
Accuracy:
10 Bit: 21 Minutes
12 Bit: 8.5 Minutes
14 Bit: 4 Minutes, 0.9 LSB or
2.6 Minutes (High Accuracy)
•
Options (Consult Factory):
Velocity
BIT: Built-In-Test
16-Bit Resolution
DESCRIPTION
The SDC-630/632/634 A/ST series are low cost, low profile Synchro-
to-Digital (S/D) and Resolver-to-Digital (R/D) tracking converters with
standard pin configurations. They use a unique control transformer
algorithm that provides inherently higher accuracy and jitter-free out-
put. Utilizing a type II servo loop, these converters have no velocity
lag up to the specified tracking rate, and output data is always fresh
and continuously available. Each unit is fully trimmed and requires no
adjustment or field calibration.
APPLICATIONS
These converters may be used wherever analog angle data from a
synchro or resolver must be rapidly and accurately converted to digi-
tal form for transmission, storage or analysis. Because these units are
extremely rugged and stable, and meet the requirements on MIL-
STD-202E, they are suitable for the most severe industrial, commer-
cial and military applications. Military ground support and avionics
uses include ordnance control, radar tracking systems, navigation
and collision avoidance systems.
* Patented
FOR MORE INFORMATION CONTACT:
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
Technical Support:
1-800-DDC-5757 ext. 7771
All trademarks are the property of their respective owners.
©
1993, 1999 Data Device Corporation
Data Device Corporation
www.ddc-web.com
INPUT OPTIONS
RESISTOR (ST)
DIVIDER
SYNCHRO INPUT OPTION (A)
S1
SIN
θ
COS
θ
RH
REF
RL
S2
S3
SCOTT-T
TRANSFORMER
RESOLVER INPUT OPTION (A)
REFERENCE (A)
ISOLATION
TRANSFORMER
DEMODULATOR
SIN
(θ
− φ)
S1
S2
SIN
θ
SIN
(θ − φ)
COS
ω
t
SIN
θ
COS
θ
COS
θ
S3
S4
RESOLVER
ISOLATION
TRANSFORMER
ERROR
PROCESSOR
AND
VOLTAGE
CONTROLLED
OSCILLATOR
VEL
VELOCITY
(OPTIONAL)
INH
INHIBIT
CB
CONVERTER
BUSY
2
SIN
θ
COS
θ
SIN
θ
COS
θ
SYNCHRO INPUT OPTION (ST)
INPUT
OPTION
S1
S2
UP-DOWN COUNTER
(CONTAINS ANGLE
φ
)
S3
SOLID STATE
SCOTT-T
BUFFER
SOLID STATE
CONTROL
TRANSFORMER
(CT)
RESOLVER INPUT OPTION (ST)
BIT 1
S1
S2
S3
S4
SOLID STATE
RESOLVER
BUFFER
BIT 10,
12 OR 14
BIT 1
(MSB)
BIT 10, 12, OR 14
(LSB)
SDC-630/632/634 A/ST
L-11/10-0
FIGURE 1. SDC-630/632/634 A/ST BLOCK DIAGRAM
TABLE 1. SDC-630/632/634 A/ST SPECIFICATIONS
PARAMETER
RESOLUTION
ACCURACY
Standard Units
High Accuracy Option
SIGNAL AND
REFERENCE INPUT
Synchro Input
90V L-L, 400 Hz
(Option H)
90V L-L, 60 Hz
(Option I)
11.8V L-L, 400 Hz
(Option L)
Resolver Input
90V L-L, 400 Hz
(Option H)
26V L-L, 60 Hz
(Option M)
11.8V L-L, 400 Hz
(Option L)
REFERENCE INPUT
Options H, I
Options M, L
VALUE
SDC-630
10 bits
±21 min
—
Signal
Frequency
Range
350-1000 Hz
47-1000 Hz
350-1000 Hz
350-1000 Hz
350-1000 Hz
350-1000 Hz
Reference
Voltage Range
40-150 Vrms
10-50 Vrms
SDC-632
12 bits
±8.5 min
—
SDC-634
14 bits
±5.3 min
±2.6 min
TABLE 1. SDC-630/632/634 A/ST SPECIFICATIONS
(CONT.)
PARAMETER
POWER SUPPLIES
Nominal Voltage
Range
Maximum Voltage
Without Damage
Current (All)
TEMPERATURE
RANGES
Operating
-1 Option
-3 Option
Storage
PHYSICAL
CHARACTERISTICS
Size (Encapsulated
Module)
Weight
-55°C to +105°C
0°C to +70°C
-55°C to +125°C
+15 V Supply
VALUE
-15 V Supply
+5 V Supply
+11 to +16.5 V -11 to -16.5 V +4.5 to +5.5 V
+18 V
20 mA
-18 V
25 mA
+7 V
10 mA
Signal Input Impedance (L-L
Balanced, Resistive)
A*
148 kΩ min
148 kΩ min
19 kΩ min
148 kΩ min
42 kΩ min
19 kΩ min
ST
123 kΩ
123 kΩ
52 kΩ
—
—
70 kΩ
3.125 x 2.625 x 0.435 inches
(7.94 x 6.67 x 1.10 cm)
4 oz
(113 gm.)
Reference Input Impedance
(Resistive)
300 kΩ min
80 kΩ min
270 kΩ
60 kΩ
NOTE: These specifications apply over temperature range, power sup-
ply range, reference frequency and amplitude range, ±10% sig-
nal amplitude variation, and up to ±10% harmonic distortion in
reference input.
POWER SUPPLIES
The main power supplies can vary over the specified ranges with
no change in converter specifications, except for a proportional
change in maximum tracking rates.
When testing or evaluating the converters, it is advisable to limit
the current in each of the supplies. Set each current limit 50%
greater than the maximum current listed for that supply as listed
in TABLE 1.
*Transformer Isolated. Other voltages and frequencies available on
special order. Transformer dielectric withstanding voltage input to out-
put is 500Vrms @ 60 Hz.
DIGITAL INPUT/
OUTPUTS
Logic Type
Inhibit Input (INH)
TTL/CMOS Compatible
Logic “0” inhibits
Does not interrupt converter tracking.
Outputs
Type
TTL/CMOS
10, 12, 14, (For 16
Consult Factory)
Parallel Data Bits Natural Binary Angle; Positive logic
Converter Busy (CB) 0.2 to 1.5 µsec positive pulse.
Data changes on leading edge.
Drive Capability
Built-In-Test (BIT)
(Special Order,
Consult Factory)
VELOCITY OUTPUT
(SPECIAL ORDER)
Polarity
Std. Voltage Range
(Full Scale)
Custom Voltage Range
BUILT IN TEST
(BIT) Special Order
Logic “0” for bit condition
See Paragraph on Bit for Conditions.
Positive Output for increasing angle
±4 Min
On request to factory. Specify: ± Voltage for
full scale
1 Std. TTL load
TIMING
FIGURE 2 shows the converter timing waveform. Whenever an
input angle change occurs, the converter changes the digital
angle in 1 LSB steps, and generates a Converter Busy (CB)
pulse. The CB is a positive pulse 0.2 to 1.5 µsec long, or 0.375µs
nominal. Data changes on the leading edge of the CB pulse, and
data can be transferred 0.5 µsec after the leading edge.
CONVERTER "1"
BUSY (CB) "0"
INHIBIT "1"
(INH) "0"
DATA
VALID
6.1 s MIN
DEPENDS ON d
dt
0.2-1.5 s
.5 s
DATA
VALID
FIGURE 2. SDC-630/632/634 A/ST TIMING DIAGRAM
3
SDC-630/632/634 A/ST
L-11/10-0
Data Device Corporation
www.ddc-web.com
TABLE 2. SDC-630/632/634 A/ST DYNAMIC CHARACTERISTICS
Bandwidth (non F carrier)
Carrier Frequency Range
Bandwidth (Closed Loop)
Ka
A1
A2
A
B
RESOLUTION
Tracking Rate (rps)
Typical
Minimum
Acceleration (1 LSB lag)
Settling Time (179° step, max)
10
28.5
24
370
500
12
7.1
6
93
600
60 HZ
47 - 1,000
15
1,100
0.1
7,600
33
16.3
14
1.8
1.5
23
900
16
0.45
0.37
5.8
2,200
10
192
160
17,000
90
400 HZ
360 - 1,000 (ST to 5,000)
100
48,000
1
48,000
220
110
12
48
40
4,220
100
14
12
10
1,050
140
16
3
2.5
260
320
UNITS
Hz
Hz
1/s
1/s
1/s
1/s
1/s
UNITS
rps
rps
°/s
2
msec
The simplest method of interfacing with a computer is to transfer
data at a fixed time interval after the Inhibit is applied. The con-
verter will ignore an Inhibit during the “busy” interval until that
interval is over. Timing is as follows: (a) apply the Inhibit, (b) wait
0.5 µsec, (c) transfer the data, (d) release the Inhibit. The Inhibit
line has no effect on converter tracking.
The closest available high grade resistor with a low temperature
coefficient of resistance should be used, and the three resistors
should be as closely matched to each other as possible. In gen-
eral, a 0.1% difference will introduce 1.7 arc minutes of addi-
tional error due to the effect on SIN/COS ratio relationship.
The ABSOLUTE value of the resistor is not critical.
In the case of the RESOLVER version (RDC), the equation is:
R
sig
= 2.2k (New L-L Voltage – Standard Unit L-L Voltage)
The calculated resistors are connected in series with S1 and S2
respectively. Note only two resistors are required. The required
resistance matching and its effect on accuracy, is the same as for
a synchro input, see FIGURE 3. The Reference Voltage is treated
in the same manner, but the value is not critical.
R
REF
= 2.8k (New Reference – Standard Reference)
For this use a 10% tolerance resistor is adequate.
SIGNAL INPUTS
To prevent damage to the inputs, the maximum steady-state volt-
age should not exceed the specified input voltage by more than
30%.
ACCOMMODATING NON-STANDARD INPUT
VOLTAGES (A ONLY)
The signal and reference input levels can be resistively scaled to
accommodate non-standard voltages, see FIGURE 3. Select a
converter that is the next lower standard voltage, and the voltage
is then scaled up by using resistors in series with the synchro
and/or reference inputs.
For a synchro input (SDC), a resistor R
sig
is added in series
with S1, S2 and S3 which is determined as follows:
R
sig
= 1.1k (New L-L Voltage – Standard Unit L-L Voltage)
That is, 1.1k for each volt above the design voltage level of
the standard unit.
Example: An SDC-634A-L (11.8 V) is to be used at 50 V L-L.
R
sig
= 1.1k (50 – 11.8) = 42.2k
NONSTANDARD
LINE-TO-LINE
LEVEL
{
{
R
SIG
R
SIG
R
SIG
S1
S2
S3
R
REF
SDC-630A
NONSTANDARD
REFERENCE
LEVEL
FIGURE 3. SDC-630/632/634 A/ST NON-STANDARD INPUT LEVEL SCALING
Data Device Corporation
www.ddc-web.com
4
SDC-630/632/634 A/ST
L-11/10-0
BUILT-IN-TEST (BIT)
Note: Special Order Request
The Built-ln-Test output (BIT) monitors the level of error from the
demodulator. This signal is the difference in the input and output
angles and ideally should be zero. However, if it exceeds approx-
imately 100 LSBs (of the selected resolution) the logic level at
BIT will change from a logic 1 to a logic 0.
A 500ms delay occurs before the excessive error bit becomes
active. The dynamic delay is responsive to the active filler loop.
This condition will occur during a large step and reset after the
converter settles out. BIT will also change to logic 0 for an over-
velocity condition, because the converter loop cannot maintain
input/output or if the converter malfunctions where it cannot
maintain the loop at a null.
BIT will also be set low for a detected total Loss-of-Signal (LOS).
The BIT signal may pulse during certain error conditions (i.e.,
converter spin around or signal amplitude on threshold of LOS).
LOS will be detected if both sin and cos input voltages are less
than 800 mV peak. The LOS has a filter on it to filter out the refer-
ence. Since the lowest specified frequency is 47hz (-27ms) the
filter must have a time constant long enough to filter this out. Time
constants of 50ms or more are possible.
Dimensions are in inches (mm).
2.625
+
0.015
-
(66.68)
14 LSB
13
12
11
10
9
8
7
6
5
4
3
BIT/VEL
+
S4
S3
0.040
+
0.002
-
(1.02)
Dia (Typ)
3.125
+
0.015
-
(79.38)
SDC-630A/ST
or
SDC-632A/ST
INH
or
+15V
SDC-634A/ST
GND
-15V
+5V
RL
RH
S2
S1
CB
0.435
(11.05)
(Max)
0.26
+
0.01
-
(6.604)
2
1 MSB
0.21
+
0.01
-
(5.334)
2.2
+
0.01
-
(55.88)
(Tol Noncum)
0.20
+
0.01
-
(5.08)
(Typ)
0.25
(6.35)
(Min)
BOTTOM VIEW
Notes:
1. BIT/VEL Pin is not present on the standard product.
For BIT/VEL output contact factory for custom part.
2. + = No Pin.
3. Serial number engraved on side of case.
SIDE VIEW
FIGURE 4. SDC-630/632/634 A/ST MECHANICAL OUTLINE
Data Device Corporation
www.ddc-web.com
5
SDC-630/632/634 A/ST
L-11/10-0
DSP 与 ARM 处理器
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