SK12429
High Frequency PLL
Frequency Synthesizer
HIGH-PERFORMANCE PRODUCTS
Description
The SK12429 is a general purpose synthesized clock
source targeting applications that require both serial
and parallel interfaces. Its internal VCO will operate
over a range of frequencies from 400 to 800 MHz.
The differential PECL output can be configured to be
the VCO frequency divided by 2, 4, 8, or 16. With the
output configured to divide the VCO frequency by 2,
and with a 16.000 MHz external quartz crystal used
to provide the reference frequency, the output frequency
can be specified in 1 MHz steps. The PLL loop filter
is fully integrated so that no external components are
required.
The internal oscillator uses the external quartz crystal
as the basis of its frequency reference. The output of
the reference oscillator is divided by 8 before being
sent to the phase detector. With a 16 MHz crystal,
this provides a reference frequency of 2 MHz. Although
this datasheet illustrates functionality only for a 16
MHz crystal, any crystal in the 10 -20 MHz range can be
used.
The VCO within the PLL operates over a range of 400
to 800 MHz. Its output is scaled by a divider that is
configured by either the serial or parallel interface.
The output of this loop divider is also applied to the
phase detector.
The phase detector and loop filter attempt to force
the VCO output frequency to be M times the reference
frequency by adjusting the VCO control voltage. Note
that for some values of M (either too high or too low)
the PLL will not achieve loop lock.
The output of the VCO is also passed through an output
divider before being sent to the PECL output driver.
This output divider (N divider) is configured through
either the serial or the parallel interfaces, and can
provide one of four division ratios (2, 4, 8, or 16).
This divider extends performance of the part while
providing a 50% duty cycle.
The output driver is driven differentially from the output
divider, and is capable of driving a pair of transmission
lines terminated in 50W to V
CC
– 2.0V. The positive
reference for the output driver and the internal logic
is separated from the power supply for the phase-
locked loop to minimize noise induced jitter.
Revision 1/January 9, 2002
1
ADVANCED
The configuration logic has two sections: serial and
parallel. The parallel interface uses the values at the
M[8:0] and N[1:0] inputs to configure the internal
counters. Normally, on system reset, the P_LOAD*
input is held LOW until sometime after power becomes
valid. On the LOW-to-HIGH transition of P_LOAD*, the
parallel inputs are captured. The parallel interface
has priority over the serial interface. Internal pull-up
resistors are provided on the M[8:0] and N[1:0] inputs
to reduce component count in the application of the
chip.
The serial interface centers on a 14-bit shift register.
The shift register shifts once per rising edge of the
S_CLOCK input. The serial input S_DATA must meet
setup and hold time as specified in the AC
Characteristics section of this document. The
configuration latches will capture the value of the shift
register on the HIGH-to-LOW edge of the S_LOAD input.
See the programming section for more information.
The TEST output reflects various internal node values,
and is controlled by the T[2:0] bits in the serial data
stream. See the programming section for more
information.
Features
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Operates from 3.0V to 5.5V Power Supply
25 to 400 MHz Differential PECL Outputs
± 25 ps Peak-to-Peak Output Jitter
Fully Integrated Phase-Locked Loop
Minimal Frequency Over-Shoot
Synthesized Architecture
Serial 3-Wire Interface
Parallel Interface for Power-Up
Quartz Crystal Interface
Available in 28-Lead PLCC Package
ESD Protection of >4000V
Industrial Temperature Range: 0
o
C to 70
o
C
flammability
moisture sensitivity
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SK12429
HIGH-PERFORMANCE PRODUCTS
Functional Block Diagram
ADVANCED
+3.3V or 5.0V
PLL_VCC
2 MHz
FREF
DIV 8
PHASE
DETECTOR
+3.3V or 5.0
VCO
4
XTAL1
OSC
5
XTAL2
OE
6
20
LATCH
28
LATCH
7
LATCH
TEST
9-BIT DIV M
COUNTER
DIV N
(2, 4, 8, 16)
24
23
FOUT
FOUT*
VCC0
25
16 MHz
400 - 800
MHz
S_LOAD
P_LOAD*
0
1
0
1
S_DATA
S_CLOCK
27
9-BIT
SR
2-BIT
SR
3-BIT
SR
26
VCC1
21
8
16
9
+3.3V or 5.0V
M[8:0]
17, 18
2
N[1:0]
22, 19
Figure 1. SK12429 Block Diagram
Revision 1/January 9, 2002
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SK12429
HIGH-PERFORMANCE PRODUCTS
PIN Description
Pin Name
Inputs
XTAL1, XTAL2
S_LOAD
(Int. Pull-down)
S_DATA
(Int. Pull-down)
S_CLOCK
(Int. Pull-down)
P_LOAD*
(Int. Pull-up)
M[8:0]
(Int. Pull-up)
N[1:0]
(Int. Pull-up)
OE
(Int. Pull-up)
Outputs
F
OUT
, F
OUT
*
TEST
Power
V
CC
PLL_V
CC
GND
This is the positive supply for the internal logic (VCC1) and the output buffer of the chip (VCC0) is connected to +3.3V
typically.
This is the positive supply for the PLL, and should be as noise-free as possible for low-jitter operation. This supply is
connected to +3.3V typically.
These pins are the negative supply for the chip and are normally all connected to ground.
These differential positive-referenced ECL signals (PECL) are the output of the synthesizer.
The function of this output is determined by the serial configuration bits T[2:0].
These pins form an oscillator when connected to an external series-resonant cr ystal.
This pin loads the configuration latches with the contents of the shift registers. The latch will be transparent when this signal
is HIGH, thus the data must be stable on the HIGH-to-LOW transition of S_LOAD for proper operation.
This pin acts as the data input to the serial configuration shift registers.
Function
ADVANCED
This pin ser ves to clock the serial configuration shift registers. Data from S_DATA is sampled on the rising edge.
This pin loads the configuration latches with the contents of the parallel inputs. The latches will be transparent when this
signal is LOW, thus the parallel data must be stable on the LOW-to-HIGH transition of P_LOAD* for proper operation.
These pins are used to configure the PLL loop divider. They are sampled on the LOW-to-HIGH transition of P_LOAD*. M[8] is
the MSB, M[0] is the LSB.
These pins are used to configure the output divider modulus. They are sampled on the LOW-to-HIGH transition of P_LOAD*.
Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of runt pulse generation of the F
OUT
output.
N[1:0]
0
0
1
1
0
1
0
1
Output Division
2
4
8
16
Function Table
Revision 1/January 9, 2002
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SK12429
HIGH-PERFORMANCE PRODUCTS
PIN Description
(continued)
ADVANCED
FOUT*
FOUT
TEST
GND
25
S_CLOCK
S_DATA
S_LOAD
PLL_V
CC
NC
NC
XTAL1
24
23
22
21
20
19
18
17
16
15
14
13
12
N[1]
N[0]
M[8]
M[7]
M[6]
M[5]
M[4]
26
27
28
1
2
3
4
5
XTAL2
6
OE
7
P_LOAD*
8
M[0]
9
M[1]
10
M[2]
11
M[3]
Figure 2. SK12429 28 PinPLCC Package
GND
VCC
VCC
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4
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SK12429
HIGH-PERFORMANCE PRODUCTS
Application Information
Programming Interface
Programming the device amounts to properly
configuring the internal dividers to produce the desired
frequency at the outputs: The output frequency can
be represented by this formula:
FOUT = (F
XTAL
÷ 8) x M ÷ N
(1)
of the fractional output frequencies achievable) will
be equal to F
XTAL
÷ 8 ÷ N.
For input reference frequencies other than 16 MHz,
the set of appropriate equations can be deduced from
equation (1). For computer applications, another useful
frequency base would be 16.666 MHz. From this
reference, one can generate a family of output
frequencies at multiples of the 33.333 MHz PCI clock.
As an example, to generate a 133.333 MHz clock
from a 16.666 MHz reference, the following M and N
values would be used:
FOUT = 16.666 ÷ 8 x M ÷ N = 2.083333 x M ÷ N
Let N = 4, M = 133.3333 ÷ 2.083333 x 4 = 256
The value for M falls within the constraints set for
PLL stability, therefore N[1:0] = 01 and M[8:0] =
10000000. If the value for M fell outside of the valid
range, a different N value would be selected to try to
move M in the appropriate direction.
The M and N counters can be loaded either through a
parallel or serial interface. The parallel interface is
controlled via the P_LOAD* signal such that a LOW to
HIGH transition will latch the information present on
the M[8:0] and N[1:0] inputs into the M and N
counters. When the P_LOAD* signal is LOW, the input
latches will be transparent and any changes on the
M[8:0] and N[1:0] inputs will affect the FOUT output
pair. To use the serial port, the S_CLOCK signal
samples the information on the S_DATA line and loads
it into a 14-bit shift register. Note that the P_LOAD*
signal must be HIGH for the serial load operation to
function. The TEST register is loaded with the first
three bits, the N register with the next two, and the M
register with the final eight bits of the data stream on
the S_DATA input. For each register, the most
significant bit is loaded first (T2, N1, and M8). A
pulse on the S_LOAD pin after the shift register is
fully loaded will transfer the divide values into the
counters. The HIGH to LOW transition on the S_LOAD
input will latch the new divide values into the counters.
Figure 3 illustrates the timing diagram for both a
parallel and a serial load of the SK12429 frequency
synthesizer.
5
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ADVANCED
Where F
XTAL
is the crystal frequency, M is the loop
divider modulus, and N is the output divider modulus.
Note that it is possible to select values of M such
that the PLL is unable to achieve loop lock. To avoid
this, always make sure that M is selected to be 200
£
M
£
400 for a 16 MHz input reference.
Assuming that a 16 MHz reference frequency is used,
the above equation reduces to:
FOUT = 2 x M ÷ N
Substituting the four values for N (2, 4, 8, 16) yields:
Table A. Output Frequency Range
N
2
4
8
16
FOUT
M
M/2
M/4
M/8
Output Frequency Range
200 - 400 MHz
100 - 200 MHz
50 - 100 MHz
25 - 50 MHz
From these ranges the user will establish the value of
N required, then the value of M can be calculated
based on the appropriate equation above. For example,
if an output frequency of 131 MHz was desired, the
following steps would be taken to identify the
appropriate M and N values. 131 MHz falls within the
frequency range set by an N value of 4 so N[1:0] =
01. For
N = 4, FOUT = M ÷ 2 and M = 2 x FOUT.
Therefore,M = 131 x 2 = 262, so M[8:0] =
100000110. Following the same procedure, a user
can generate any whole frequency desired between
25 and 400 MHz. Note that for N > 2, fractional
values of FOUT can be realized. The size of the
programmable frequency steps (and thus the indicator
Revision 1/January 9, 2002
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