SiS5597 SiS5598 Pentium PCI/ISA Chipset
1. Introduction
Nowadays, several PC form factors exist in the PC board market, such as NLX, LPX, ATX
and Baby-AT form factors. Due to the different placements of the form factor, PC chipsets
should be prepared for different board layouts. As a result, SiS chips based on compatible logic
design provide two series of chipsets, SiS 5597 and SiS 5598, to assist board designers for
their board layouts.
SiS 5597’s pin assignment is based on NLX, and LPX form factor, while SiS 5598’s is defined
on the basis of ATX and Baby-AT form factors. In the next few chapters, you will read “SiS
Chip” which indicates either SiS 5597 or 5598 chipsets, decided by the placements of form
factors on PC boards of customers.
The SiS Chip with built-in VGA controller is a highly integrated single chip solution for
Pentium PCI/ISA system. A portion of on-board DRAM is shared with the integrated VGA
controller. In that way, the system cost is substantially reduced and on-board DRAM can be
used flexibly.
The SiS Chip consists of Host-to-PCI bridge function, PCI to ISA bridge function, PCI IDE
function, Universal Serial Bus host/hub function, Integrated RTC, Integrated Keyboard
Controller and Graphics/Video accelerate function.
SiS Chip supports Enhanced Power Management, including legacy Power Management Unit
and Advanced Configuration and Power Interface (ACPI). It also supports ATA Synchronous
DMA transfer protocol to improve the IDE performance and Common Architecture for
moving ISA function to PCI to improve system performance. The system block diagram is
shown below :
PBSRAM
CPU
Host Address
Host Data Bus
Tag
RAM
MD Bus
244 x 2
(optional)
DRAM
MA Bus
Master IDE
FC
SiS Chip
USB x 2
GPIO
Keyboard
MONITOR
BIOS
KBC
(optional)
245 x4
ISA Bus
PCI Bus
ISA
Device
ISA
Device
ISA
Device
ISA
Device
PCI
Device
PCI
Device
PCI
Device
PCI
Device
Preliminary V2.0 April 15, 1997
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Silicon Integrated Systems Corporation
SiS5597 SiS5598 Pentium PCI/ISA Chipset
2. Features
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Support Intel Pentium CPU and other compatible CPU host bus at 50/55/60/66/75
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MHz
Support CPU with MMX feature
Support the Pipelined Address Mode of Pentium CPU
Support the Full 64-bit Pentium Processor data Bus
Meet PC97 Requirements
Integrated Second Level ( L2 ) Cache Controller
- Write Back Cache Modes
- 8 bits or 7 bits Tag with Direct Mapped Cache Organization
- Integrated 16K bits Dirty RAM
- Support Pipelined Burst SRAM
- Support 256 KBytes and 512 KBytes Cache Sizes
- Cache Hit Read/Write Cycle of 3-1-1-1
- Cache Back-to-Back Read/Write Cycle of 3-1-1-1-1-1-1-1
Integrated DRAM Controller
- Support 6 RAS lines (3 Banks) of FPM/EDO/SDRAM DIMMs/SIMMs
- Support 2Mbytes to 384Mbytes of main memory
- Support Cacheable DRAM Sizes up to 128 MBytes.
- Support 256K/512K/1M/2M/4M/8M/16M/32M x N FPM/EDO/SDRAM DRAM
- Support 64 Mb DRAM Technology
- Support 3.3V or 5V DRAM.
- Supports Symmetrical and Asymmetrical DRAM.
- Support 32 bits/64 bits mixed mode configuration
- Support Concurrent Write Back
- Support CAS before RAS Refresh
- Support Relocation of System Management Memory
- Programmable CAS#, RAS#, RAMWE# and MA Driving Current.
- Fully Configurable for the Characteristic of Shadow RAM ( 640 KBytes to 1 MBytes)
- Support FPM DRAM 5-3-3-3(-3-3-3-3) Burst Read Cycles
- Support EDO DRAM 5-2-2-2(-2-2-2-2) Burst Read Cycles
- Support SDRAM 6-1-1-1(-2-1-1-1) Burst Read Cycles
- Support X-1-1-1/X-2-2-2/X-3-3-3 Burst Write Cycles
- Support 8 Qword Deep Buffer for Read/Write Reordering, Dword Merging and 3/2-1-1-
1 Post write Cycles
- Two Programmable Non-Cacheable Regions
- Option to Disable Local Memory in Non-Cacheable Regions
- Shadow RAM in Increments of 16 KBytes
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Silicon Integrated Systems Corporation
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Preliminary V2.0 April 15, 1997
SiS5597 SiS5598 Pentium PCI/ISA Chipset
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Integrated PMU Controller
- Meet ACPI Requirements
- Support Both ACPI and Legacy PMU
- Support Suspend to Disk
- Support SMM Mode of CPU
- Support CPU Stop Clock
- Support Power Button for ACPI function
- Support Automatic Power Control for system power off function
- Support Modem Ring-in, RTC Alarm Wake up
- Support Thermal Detection
- Support GPIOs, and GPOs for External Devices Control
- Support Programmable Chip Select
Provides High Performance PCI Arbiter.
- Support up to 4 PCI Masters
- Support Rotating Priority Mechanism
- Hidden Arbitration Scheme Minimizes Arbitration Overhead.
- Support Concurrency between CPU to Memory and PCI to PCI.
Integrated Host-to-PCI Bridge
- Support Asynchronous and Synchronous PCI Clock
- Translates the CPU Cycles into the PCI Bus Cycles
- Provides CPU-to-PCI Read Assembly and Write Disassembly Mechanism
- Translates Sequential CPU-to-PCI Memory Write Cycles into PCI Burst Cycles
- Zero Wait State Burst Cycles
- Support IDE Posted Write
- Support Pipelined Process in CPU-to-PCI Access
- Support Advance Snooping for PCI Master Bursting
- Maximum PCI Burst Transfer from 256 Bytes to 4 KBytes
Integrated Posted Write Buffers and Read Prefetch Buffers to Increase System
Performance
- CPU-to-Memory Posted Write Buffer (CTMFF) with 8 QW Deep, Always Sustains 0
Wait Performance on CPU-to-Memory.
- CPU-to-Memory Read Buffer with 4 QW Deep
- CPU-to-PCI Posted Write Buffer(CTPFF) with 8 DW Deep
- PCI-to-Memory Posted Write Buffer(PTHFF) with 8 QW Deep, Always Streams 0 Wait
Performance on PCI-to/from-Memory Access
- PCI-to-Memory Read Prefetch Buffer(CTPFF) with 8 QW Deep
Integrated Video/Graphics Accelerator
- Support 32-bit PCI local bus standard revision 2.1
- Built-in an enhanced 64-bit BITBLT graphics engine
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Silicon Integrated Systems Corporation
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Preliminary V2.0 April 15, 1997
SiS5597 SiS5598 Pentium PCI/ISA Chipset
- Support tightly coupled host interface to VGA to speed up GUI performance and the
video playback frame rate
- Support direct access to video memory to speed up GUI performance and the video
playback frame rate
- Shared System Memory Area 0.5MB, 1MB, 1.5MB, 2MB, 2.5MB, 3MB, 3.5MB, 4MB
- Built-in programmable 24-bit true-color RAMDAC with reference-voltage generator
- Built-in dual-clock generator
- Built-in monitor-sense circuit
- Built-in Phillips SAA7110/SAA7111, Brooktree Bt815/817/819A(8 -bit SPI mode 1,2)
video decoder interface
- Built-in Standard feature connector logic support
Integrated PCI-to-ISA Bridge
- Translates PCI Bus Cycles into ISA Bus Cycles
- Translates ISA Master or DMA Cycles into PCI Bus Cycles
- Provides a Dword Post Buffer for PCI to ISA Memory cycles
- Two 32 bit Prefetch/Post Buffers Enhance the DMA and ISA Master Performance
- Fully Compliant to PCI 2.1
Enhanced DMA Functions
- 8-, 16- bit DMA Data Transfer
- ISA compatible, and Fast Type F DMA Cycles
- Two 8237A Compatible DMA Controllers with Seven Independent Programmable
Channels
- Provides the Readability of the two 8237 Associated Registers
- Support Distributed DMA
Built-in Two 8259A Interrupt Controllers
- 14 Independently Programmable Channels for Level- or Edge-triggered Interrupts
- Provides the Readability of the two 8259A Associated Registers
- Support Serial IRQ
Three Programmable 16-bit Counters compatible with 8254
- System Timer Interrupt
- Generates Refresh Request
- Speaker Tone Output
- Provides the Readability of the 8254 Associated Registers
Built-in Keyboard Controller
- Hardwired Logic Provides Instant Response
- Support PS/2 Mouse interface
- Support Hot Key "Wake-up" Function
- Capable of Enable/Disable Internal KBC and PS2 Mouse
Built-in Real Time Clock(RTC) with 256B CMOS SRAM
- Built-in up to one Month Alarm for ACPI
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Silicon Integrated Systems Corporation
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Preliminary V2.0 April 15, 1997
SiS5597 SiS5598 Pentium PCI/ISA Chipset
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Fast PCI IDE Master/Slave Controller
- Bus Master Programming Interface for ATA Windows 95 Compliant Controller
- Support PCI Bus Mastering
- Plug and Play Compatible
- Support Scatter and Gather
- Support Dual Mode Operation - Native Mode and Compatibility Mode
- Support IDE PIO Timing Mode 0, 1, 2 ,3 and 4
- Support Multiword DMA Mode 0, 1, 2
- Support Ultra DMA/33
- Two Separate IDE Bus
- Two 16 Dword FIFO for PCI Burst Transfers.
Universal Serial Bus Host Controller
- OpenHCI Host Controller with Root Hub
- Two USB ports
- Support Legacy Devices
- Support Over Current Detection
Support I2C serial Bus
Support the Reroutibility of the four PCI Interrupts
Support 2Mb Flash ROM Interface
Support Signature Analysis for automatic test for VGA controller
Support NAND Tree for ball connectivity testing
553-Balls BGA Package
0.35µm 3.3V Technology
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2.1 Detail Features for Integrated Video/Graphics Accelerator
Host Bus Interface
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Support tightly couppled host interface to VGA to speed up GUI performance and
the video playback frame rate
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Support direct access to video memory to speed up GUI performance and the video
playback frame rate
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Shared System Memory Area 0.5MB, 1MB, 1.5MB, 2MB, 2.5MB, 3MB, 3.5MB,
4MB
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Built-in 8QW CPU post write buffer with byte merging capability
PCI Bus Interface
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Support 32-bit PCI local bus standard revision 2.1
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Support PCI burst write
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Support PCI multimedia design guide Rev. 1.0
Preliminary V2.0 April 15, 1997
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Silicon Integrated Systems Corporation
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