®
DEVICE SPECIFICATION
BiCMOS PECL CLOCK GENERATOR
FEATURES
• Generates six clock outputs from 20 MHz to 80
MHz (HFOUT operates from 10 MHz to 40 MHz)
• Allows PECL or TTL reference input
• Provides differential PECL output at up to 160
MHz
• 21 selectable phase/frequency relationships for
the clock outputs
• Compensates for clock skew by allowing output
delay adjustment down to 3.125 ns increments
• TTL outputs have less than 400 ps maximum
skew
• Lock Detect output indicates loop status
• Internal PLL with VCO operating at 160 to 320
MHz
• Test Enable input allows VCO bypass for open-
loop operation
• Maximum 1.0 ns of phase error (750 ps from
part to part)
• Proven 1.0 micron BiCMOS technology
• Single +5V power supply operation
• 44 PLCC package
S4405
APPLICATIONS
• CMOS ASIC Systems
• High-speed Microprocessor Systems
• Backplane Clock Deskew and Distribution
GENERAL DESCRIPTION
The S4405 BiCMOS clock generators allow the user
to generate multiphase TTL clocks in the 10–80 MHz
range with less than 400 ps of skew. Use of a simple
off-chip filter allows an entire 160–320 MHz phase-
locked loop (PLL) to be implemented on-chip. Divide-
by-two and times-two outputs allow the ability to
generate output clocks at half, equal to, or twice the
reference clock input frequency. The reference is se-
lectable to be either TTL or PECL. By using the pro-
grammable divider and phase selector, the user can
select from up to 21 different output relationships.
The outputs can be phase-adjusted in increments as
small as 3.125 ns to tailor the clocks to exact system
requirements.
Implemented in AMCC’s proven 1.0 micron BiCMOS
technology, the S4405 generates six TTL outputs
and one differential PECL output. Output enables are
provided for the various TTL banks, allowing clock
control for board and system tests.
Figure 1. Clock Generator Block Diagram
TTLREF
PECLREFP
PECLREFN
I
0
I
1
S
MUX
REFCLK
PHASE
DETECTOR
CHARGE
PUMP
LOCK
14KΩ
INPSEL
FBCLK
FILTER
VCO
PECLP
PECLN
X2FOUT
HFOUT
÷2
I
0
I
1
MUX
TSTEN
FOUT0
DIVIDER
AND
PHASE
CONTROL
LOGIC
SELECT
FOUT1
Digital
+5V
0V
DIVSEL
PHSEL0
PHSEL1
RESET
FOUT3
FOUT2
Analog
+5V
0V
OUTEN0
OUTEN1
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
Page 1
S4405
FUNCTIONAL DESCRIPTION
This BiCMOS clock generator is designed to allow
the user to generate TTL clocks, in the 10–80 MHz
range, with less than 400 ps of skew. Implemented
in AMCC’s 1.0µ BiCMOS technology, the internal
VCO, phase detector, and programmable divider and
phase selector allow the user to tailor the TTL output
clocks for his/her system needs. The internal VCO
can operate between 160 to 320 MHz, and the pro-
grammability allows the user to generate TTL output
clocks in the 10–80 MHz range, and a differential
+5V referenced ECL output at 80–160 MHz.
The clock generator offers the user the ability to se-
lect the appropriate phase relationship among the
four FOUT0–3 TTL clock outputs. The phase selec-
tion choices are shown in Table 2.
The clock generator also allows the user to choose
the divide-by ratio between the VCO frequency and
the frequency of the FOUT0–3 signals. The VCO fre-
quency can be divided by 4 when DIVSEL is low, and
divided by 8 when DIVSEL is high. The divide ratio
between the VCO and the pseudo ECL outputs,
PECLP and PECLN, is a fixed divide-by-2.
The clock generator also has two output enable in-
puts which can be used to control which outputs
toggle. OUTEN0 controls the HFOUT and X2FOUT
outputs, and OUTEN1 controls the FOUT0–3 out-
puts. When the output enables are high, the outputs
are disabled, and held in a high state.
REFCLK can be driven by either the TTLREF or
PECLREF inputs. The reference clock source is se-
lected with the INPSEL input. When INPSEL is low,
the TTLREF input is selected as the reference clock.
The FOUT0–3 outputs are the main TTL output
clocks that the generator supplies. The frequency of
these outputs is determined by the REFCLK clock
frequency and the output clock that is tied to the
FBCLK input. FOUT0–3 will be equal to REFCLK,
half of REFCLK, or twice the frequency of REFCLK.
The X2FOUT TTL output provides a clock signal that
is identical to the FOUT0 output in the divide-by-4
Table 1. Example Phase Resolution
FUNCTIONAL DESCRIPTION
mode, but twice the FOUT0 frequency (max. freq. of
66 MHz) in the divide-by-8 mode. The HFOUT TTL
output provides a clock signal that is also in phase with
the FOUT0 output, but at half the FOUT0 frequency.
FILTER is the analog signal from the phase detector
going into the VCO. This pin is provided so a simple
external filter (a single resistor and one capacitor)
can be included in the phase-locked loop of the clock
generator.
The LOCK output goes high when the reference
clock and FBCLK are within 2–4 ns of each other.
This output tells the user that the PLL is in lock.
Three pins are included for test purposes. TESTEN
allows the chip to use the REFCLK signal instead of
the VCO output to clock the chip. This is used during
chip test to allow the counters and control logic to be
tested independently of the VCO. The RESET pin
initializes the internal counter flip-flops to zeros, but
several clock cycles are necessary before the out-
puts go to a zero state.
The minimum phase delay between FOUT0–3 sig-
nals is a function of the VCO frequency. The VCO
frequency can be determined by multiplying the out-
put frequency by the divide-by ratio of four or eight.
The minimum phase delay is equal to the period of
the VCO frequency: M
P
= 1/VCO freq. Since the VCO
can operate in the 160 MHz to 320 MHz range, the
range of minimum phase delay values is 6.25 ns to
3.125 ns. Table 1 shows various FOUT/VCO fre-
quencies and the associated phase resolution.
The charge pump and VCO portion of the chip use a
separate analog power supply. This supply is brought
onto the chip through a distinct set of power and
ground pins. This supply should be free of digital
switching noise.
Example:
In a typical system, designers may need several low-
skew outputs, one early clock, one late clock, a clock
at half the input clock frequency, and one at twice
the input clock frequency. This system requirement
Table 2. Phase Selections
FOUT0–3
Freq
80 MHz
66 MHz
50 MHz
40 MHz
40 MHz
33 MHz
25 MHz
20 MHz
Divider
Select
4
4
4
4
8
8
8
8
VCO
Freq
320 MHz
266 MHz
200 MHz
160 MHz
320 MHz
266 MHz
200 MHz
160 MHz
Min Phase
Resolution
3.125 ns
3.75 ns
5.0 ns
6.25 ns
3.125 ns
3.75 ns
5.0 ns
6.25 ns
PHSEL1 PHSEL0
0
0
1
0
1
0
Phase Relationship
All at same phase
Outputs skewed by 90 degrees from
each other
FOUT1 leads FOUT0 by minimum
phase, FOUT2 lags FOUT0 by
minimum phase, and FOUT3 lags
FOUT0 by 90 degrees
Outputs skewed by minimum phase
(determined by the divider selection,
and the VCO frequency) from each
other.
1
1
Note:
The PECL output is not affected by the phase select inputs.
Page 2
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
FUNCTIONAL DESCRIPTION
can be met by setting PHSEL1 to 1, PHSEL0 to 0,
and feeding back FOUT0 to the FBCLK input (Row
10 of Table 3). The result is that FOUT0 will be
phase-aligned to the reference clock, FOUT1 will
lead the reference clock by a minimum phase delay,
FOUT2 will lag the reference clock by a minimum
phase delay, FOUT3 will phase-lag the reference
clock by 90°, HFOUT will be phase-aligned with the
reference clock but at half the frequency, and
X2FOUT will be either phase-aligned at the same
frequency as the reference clock if DIVSEL = 0, or at
twice the frequency if DIVSEL = 1.
Enabling Outputs
The S4405 has two output-enable inputs that control
which outputs toggle. When held LOW, OUTEN0
controls the frequency doubler output X2FOUT and
the half-frequency output HFOUT. OUTEN1 controls
the FOUT0–3 outputs. When an output enable pin is
held High, its associated outputs are disabled and
held in a High state.
Filter
The FILTER output is a tap between the analog out-
put of the phase detector and the VCO input. This pin
allows a simple external filter (Figure 2) to be in-
cluded in the PLL. AMCC recommends the use of the
filter component values shown. This filter was chosen
for its ability to reduce the output jitter and filter out
noise on the reference clock input.
Reset
When the RESET pin is pulled low, all the internal
states go to zero, but the outputs will not go low until
one clock cycle later (VCO/2 or period of the refer-
ence clock). After the chip is reset, the PLL requires
a resynchronization time before lock is again achieved.
Lock Detect
A lock detect function is provided by the LOCK out-
put. When the selected reference clock and FBCLK
S4405
are within 2–4 ns of each other, the PLL is in lock,
and the LOCK output goes High.
Power Supply Considerations
Power for the analog portion of the S4405 chips must
be isolated from the digital power supplies to mini-
mize noise on the analog power supply pins. This
isolation between the analog and digital power sup-
plies can be accomplished with a simple external
power supply filter (Figure 3). The analog power
planes are connected to the digital power planes
through single ferrite beads (FB1 and FB2) or induc-
tors capable of handling 25 mA. The recommended
value for the inductors is in the range from 5 to
100µH, and depends upon the frequency spectrum of
the digital power supply noise. The ferrite beads
should exhibit 75Ω impedance at 10 MHz.
Decoupling capacitors are also very important to
minimize noise. The decoupling capacitors must
have low lead inductance to be effective, so ceramic
chip capacitors are recommended. Decoupling ca-
pacitors should be located as close to the power pins
as physically possible. And the decoupling should be
placed on the top surface of the board between the
part and its connections to the power and ground
planes.
BOARD LAYOUT CONSIDERATIONS
• The S4405 is sensitive to noise on the Analog +5 V
and Filter pins. Care should be taken during board
layout for optimum results.
• All decoupling capacitors (C1–C4 = 0.1
µF)
should
be bypassed between VCC and GND, and placed as
close to the chip as possible (preferably using ce-
ramic chip caps) and placed on top of board between
S4405 and the power and ground plane connections.
• No dynamic signal lines should pass through or
beneath the filter circuitry area (enclosed by dashed
lines in Figure 4) to avoid the possibility of noise due
to crosstalk.
Figure 2. External PLL Filter
32
A VCC
A +5V
0.1 µF
Figure 3. External Power Supply Filter
FB1
ANALOG +5V
0.1 µF
DIGITAL +5V
10 µF
Tantalum
(optional)
DIGITAL GND
S4405
1.5k
Ω
FILTER
31
ANALOG GND
FB2
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
Page 3
S4405
• The analog VCC supply can be a filtered digital
VCC supply as shown below. The ferrite beads or
inductors, FB1 and FB2, should be placed within
three inches of the chip.
• The analog VCC plane should be separated from the
digital VCC and ground planes by at least 1/8 inch.
Figure 4. Board Layout
PIN DESCRIPTIONS
PHSEL0.
This input, along with PHSEL1, allows se-
lection of the phase relationship among the four
FOUT0–FOUT3 outputs. See Tables 2 and 3 for the
selection choices.
PHSEL1.
Along with PHSEL0, allows selection of the
phase relationship among the four FOUT0–FOUT3
outputs. See Tables 2 and 3 for the selection
choices.
OUTEN0.
Active Low. Output enable signal that con-
trols which outputs toggle. Controls the frequency
doubler output (X2FOUT) and the half-frequency out-
put (HFOUT).
D +5V
FB1
0.1µF
1.5KΩ
A +5V
D GND
A GND
34
S4405
33
32
31
0.1µF
FB2
OUTEN1.
Active Low. Output enable signal that con-
trols which outputs toggle. Controls the FOUT0–
FOUT3 outputs.
RESET.
Active Low. Initializes internal states for test
purposes.
TSTEN.
Active High. Allows REFCLK to drive the
divider phase adjust circuitry, after the first divide-by-
two stage. Therefore, REFCLK can be divided by two
in the divide-by-four mode, and divided by four in the
divide-by-eight mode, and used to directly sequence
the outputs.
INPSEL.
Allows user to select between TTLREF and
PECLREF reference frequencies. When INPSEL is
High, the PECLREF input is selected.
Test Capabilities
The TSTEN input allows users to bypass the VCO and
provide their own clock through the selected reference
clock input. When TSTEN is High, the VCO is turned
off and the REFCLK signal drives the divider/phase
adjust circuitry, directly sequencing the outputs. The
TSTEN and REFCLK inputs join the divider circuitry
after the initial divide-by-two stage. Therefore, REFCLK
is divided by two in the divide-by-four mode and di-
vided by four in the divide-by-eight mode.
Output Signals
FILTER.
A tap between the analog output of the
phase detector and the VCO input. Allows a simple
external filter (a single resistor and capacitor) to be
included in the PLL.
X2FOUT.
Provides a clock signal identical to the
FOUT0 output in the divide-by-four mode and twice
the FOUT0 frequency (maximum of 80 MHz) in the
divide-by-eight mode.
FOUT0.
Clock output.
FOUT1.
Clock output.
FOUT2.
Clock output.
FOUT3.
Clock output.
HFOUT.
Provides a clock signal in phase with the
FOUT0 output, but at half the FOUT0 frequency in
both the divide-by-four and divide-by-eight modes.
PECLP/N.
Differential PECL output, always one-half
the VCO frequency.
LOCK.
Goes high when the reference clock and
FBCLK are within 2–4 ns of each other, demonstrat-
ing that the PLL is in lock.
PIN DESCRIPTIONS
Input Signals
TTLREF.
TTL. Frequency reference supplied by the
user that, along with the output tied to the FBCLK
input, determines the frequency of the FOUT0–
FOUT3 outputs. INPSEL is used to select between
this reference and the PECL reference PECLREFP/N.
PECLREFP/N.
Differential PECL. Frequency refer-
ence supplied by the user. Selectable by the INPSEL
input.
FBCLK.
Feedback clock that, along with the refer-
ence clock input, determines the frequency of the
FOUT0–FOUT3 outputs. One output is selected to
feed back to this input. (See Table 3.)
DIVSEL.
Controls the divider circuit that follows the
VCO. When DIVSEL is low, the VCO frequency is
divided by four. When DIVSEL is high, the VCO fre-
quency is divided by eight. (See Tables 1 and 3.)
Page 4
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
OUTPUT SELECT MATRIX
Table 3. Output Select Matrix
Configuration
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
S4405
Select Pins
PHSEL1 PHSEL0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
Output Fed
to FBCLK
FOUT0–FOUT3
HFOUT
X2FOUT (÷8)
FOUT0
FOUT1
FOUT2
FOUT3
HFOUT
X2FOUT (÷8)
FOUT0
FOUT1
FOUT2
FOUT3
HFOUT
X2FOUT (÷8)
FOUT0
FOUT1
FOUT2
FOUT3
HFOUT
X2FOUT (÷8)
Output Phase Relationships
FOUT0 FOUT1
0
2(0)
0/2
0
–Q
–2Q
–3Q
2(0)
0/2
0
t
–t
–Q
2(0)
0/2
0
–t
–2t
–3t
2(0)
0/2
0
2(0)
0/2
Q
0
–Q
–2Q
2(Q)
Q/2
–t
0
–2t
–Q–t
2(–t)
–t/2
t
0
–t
–2t
2(t)
t/2
÷
4
0
2(0)
0/2
3Q
2Q
Q
0
2(3Q)
3Q/2
Q
Q+t
Q–t
0
2(Q)
Q/2
3t
2t
t
0
2(3t)
3t/2
0/2
0
0/4
0/2
–Q/2
–2Q/2
–3Q/2
0
0/4
0/2
t/2
–t/2
–Q/2
0
0/4
0/2
–t/2
–2t/2
–3t/2
0
0/4
0
2(0)
0
–Q
–2Q
–3Q
2(0)
0
t
–t
–Q
2(0)
0
–t
–2t
–3t
2(0)
÷
8
2(0)
4(0)
0
2(0)
2(–Q)
2(–2Q)
2(–3Q)
4(0)
0
2(0)
2(t)
2(–t)
2(–Q)
4(0)
0
2(0)
2(–t)
2(–2t)
2(–3t)
4(0)
0
FOUT2 FOUT3 HFOUT
0
2(0)
0/2
2Q
Q
0
–Q
2(2Q)
2Q/2
t
2t
0
–Q+t
2(t)
t/2
2t
t
0
–t
2(2t)
2t/2
X2FOUT
Notes:
1. “0” implies the output is aligned with the reference clock.
2. “t” implies the output lags the reference clock by a minimum phase delay.
3. “Q” implies the output lags the reference clock by 90° of phase.
4. “–t” implies the output leads the reference clock by a minimum phase delay.
5. “–Q” implies the output leads the reference clock by 90° of phase.
6. “2( )” implies the output is at twice the frequency of the reference clock.
7. “/2” implies the output is at half the frequency of the reference clock.
8. The PECLN/P Differential PECL output is not affected by the PHSEL inputs.
Legend
Table
entry
Waveform
Table
entry
Waveform
Table
entry
Waveform
TTLREF
0
t
2t
–t
–t 0 t 2t
TTLREF
Q
2Q
–Q
TTLREF
2(0)
0/2
4(0)
0/4
–90° 0° 90° 180°
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
Page 5
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