LV77D Series 1.8 V
LVDS Clock Oscillators
December 2006
• Pletronics’ LV77D Series is a quartz crystal
controlled precision square wave generator with
an LVDS output.
• The package is designed for high density surface
mount designs.
• Low cost mass produced oscillator.
• Tape and Reel or cut tape packaging is available.
• 5 x 7 mm LCC Ceramic Package
• Enable/Disable Function on pad 1
• Low Jitter
Pletronics Inc. certifies this device is in accordance with the
RoHS 6/6 (2002/95/EC) and WEEE (2002/96/EC) directives.
Pletronics Inc. guarantees the device does not contain the following:
Cadmium, Hexavalent Chromium, Lead, Mercury, PBB’s, PBDE’s
Weight of the Device: 0.16 grams
Moisture Sensitivity Level: 1 As defined in J-STD-020C
Second Level Interconnect code: e4
Absolute Maximum Ratings:
Parameter
V
CC
Supply Voltage
Vi
Vo
Input Voltage
Output Voltage
Unit
-0.5V to +5.0V
-0.5V to V
CC
+ 0.5V
-0.5V to V
CC
+ 0.5V
Thermal Characteristics
The maximum die or junction temperature is 155
o
C
The thermal resistance junction to board is 30 to 50
o
C/Watt depending on the solder pads, ground plane
and construction of the PCB.
Product information is current as of publication date. The product conforms
to specifications per the terms of the Pletronics standard warranty. Production
processsing does not necessarily include testing of all parameters.
Copyright © 2005, 2006, Pletronics Inc.
LV77D Series 1.8 V
LVDS Clock Oscillators
December 2006
Part Number:
LV77
45
D
E
X
-125.0M
-XX
Packaging code or blank
T250 = 250 per Tape and Reel
T500 = 500 per Tape and Reel
T1K = 1000 per Tape and Reel
Frequency in MHz
Supply Voltage V
CC
X
= 1.8V _ 10%
+
Optional Enhanced OTR
E
= Temperature range -40 to +85
o
C
Series Model
Frequency Stability
45
= _ 50 ppm
+
44
= _ 25 ppm
+
20
= _ 20 ppm
+
Series Model
Marking Legend:
PLE = Pletronics
FF.FFF
M = Frequency in MHz
YYWW or YWW or
YMD
= Date of Manufacture (year and week, or year-month-day)
All other marking is internal factory codes
Specifications such as frequency stability, supply voltage and operating temperature range, etc. are
not identified from the marking. External packaging labels and packing list will correctly identify the
ordered Pletronics part number.
Codes for Date Code YMD
Code
Year
Code
Month
Code
Day
Code
Day
Code
Day
1
1
D
13
T
25
6
2006
A
JAN
2
2
E
14
U
26
7
2007
B
FEB
3
3
F
15
V
27
8
2008
C
MAR
4
4
G
16
W
28
9
2009
D
APR
E
MAY
5
5
H
17
X
29
0
2010
F
JUN
6
6
J
18
Y
30
1
2011
G
JUL
7
7
K
19
Z
31
H
AUG
8
8
L
20
2
2012
J
SEP
9
9
M
21
K
OCT
A
10
N
22
L
NOV
B
11
P
23
M
DEC
C
12
R
24
Part Marking:
PLE LV77
FF.FFF
M
C
YMDXX
or
LV7XYWWXX
FF.FFF
M
C
PLE XXX
www.pletronics.com
425-776-1880
2
LV77D Series 1.8 V
LVDS Clock Oscillators
December 2006
Electrical Specification for 1.80V +5% over the specified temperature range and
_
the frequency range of 1 to 250 MHz
Item
Frequency Accuracy “45"
“44"
“20"
Output Waveform
Differential Output (V
OD
)
200
0.81
--
45
300
400
Jitter
Vcc Supply Current
Enable/Disable Internal Pull-up
V disable
V enable
Output leakage
Enable
Disable time
Start up time
Operating Temperature Range
Storage Temperature Range
Standby Current I
CC
V
OUT
= V
CC
V
OUT
= 0V
-
-
-
50
-
1.54
-20
-20
-
-
-
-
0
-40
-55
2
Min
-50
-25
-20
Max
+50
+25
+20
LVDS
450
1.38
50
55
700
900
0.6
2.8
35
-
0.18
-
+20
+20
10
10
5
3
+70
+85
+125
3
mA
Kohm
Volts
Volts
uA
uA
nS
nS
mS
mS
o
o
o
Unit
ppm
Condition
For all supply voltages, load changes, aging for 1
year, shock, vibration and temperatures
mVolts
Volts
mVolts
%
pS
pS
pS RMS
Referenced to 50% of amplitude or crossing point
> 80 MHz
< 80 MHz
Vth is 20% and 80% of waveform
See load circuit
R1 = 50 ohms
*
Output Offset Voltage (V
OS
)
Differential Output Error (dV
OS
)
Output Symmetry
Output T
RISE
and T
FALL
Measured from 12KHz to 20MHz from Fnominal
Measured from 10Hz to 1MHz from Fnominal
Includes current of properly terminated device
To Vcc (equivalent resistance)
Referenced to Ground
Pad 1 low, device disabled
Time for output to reach a logic state
Time for output to reach a high Z state
> 80 MHz
< 80 MHz
Measured from the time
Vcc = 2.2V
C
C
C
Standard Temperature Range
Extended Temperature Range
Pad 1 low, device disabled
“E” Option
mA
*
Output Offset Voltage is within proper range of LVDS inputs
Specifications with Pad 1 E/D open circuit
www.pletronics.com
425-776-1880
3
LV77D Series 1.8 V
LVDS Clock Oscillators
December 2006
Typical Phase-Noise Response
0
-20
-40
dBc/Hz
-60
-80
-100
-120
-140
-160
10
1,000
100,000
10,000,000
Frequency (Hz)
Load Circuit
Test Waveform
Symmetry
Vhigh
80%
50%
20%
Vlow
Trise
Tfall
Out
Out*
Showing Out Measurement only
www.pletronics.com
425-776-1880
4
LV77D Series 1.8 V
LVDS Clock Oscillators
December 2006
Reliability
: Environmental Compliance
Parameter
Mechanical Shock
Vibration
Solderability
Thermal Shock
Condition
MIL-STD-883 Method 2002, Condition B
MIL-STD-883 Method 2007, Condition A
MIL-STD-883 Method 2003
MIL-STD-883 Method 1011, Condition A
ESD Rating
Model
Human Body Model
Charged Device Model
Minimum Voltage
1500
1000
Conditions
MIL-STD-883 Method 3115
JESD 22-C101
Package Labeling
Label is 1" x 2.6" (25.4mm x 66.7mm)
Font is Courier New
Bar code is 39-Full ASCII
Label is 1" x 2.6" (25.4mm x 66.7mm)
Font is Arial
www.pletronics.com
425-776-1880
5
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