DATA SHEET
MOS Integrated Circuit
µ
PD16715
384 OUTPUT TFT-LCD SOURCE DRIVER
(COMPATIBLE WITH 64 GRAY SCALES)
The
µ
PD16715 is a source driver for TFT-LCDs capable of dealing with displays with 64 gray scales. Data input is
based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors
by output of 64 values
γ
- corrected by an internal D/A converter and 5-by-2 external power modules. Because the
output dynamic range is as large as 13.3 V
P-P
, level inversion operation of the LCD’s common electrode is rendered
unnecessary. Also, to be able to deal with dot-line inversion when mounted on a single side, this source driver is
equipped with a built-in 6-bit D/A converter circuit whose odd output pins and even output pins respectively output
gray scale voltages of differing polarity. Assuring a maximum clock frequency of 55 MHz when driving at 3.0 V, this
driver is applicable to XGA/SXGA-standard TFT-LCD panels.
FEATURES
• Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter
• Output dynamic range 13.3 V
P-P
min. (@ V
DD2
= 13.5 V)
• CMOS level input
• Input of 6 bits (gradation data) by 6 dots
• High-speed data transfer: fmax. = 55 MHz (internal data transfer speed when operating at 3.0 V)
• 384 outputs
• Apply for only dot-line inversion
• Display data inversion function (POL2)
• Single bank arrangement is possible (loaded with slim TCP)
ORDERING INFORMATION
Part Number
Package
TCP (TAB package)
µ
PD16715N-
× × ×
The TCP’s external shape is customized. To order your TCP’s external shape, please contact a NEC salesperson.
Document No. S13288EJ1V0DS00 (1st edition)
Date Published August 1998 N CP(K)
Printed in Japan
©
1998
µ
PD16715
1. BLOCK DIAGRAM
STHR
R/L
CLK
STB
C
1
C
2
64-bit bidirectional shift register
C
63
C
64
STHL
V
DD1
V
SS1
D
00 - 05
D
10 - 15
D
20 - 25
D
30 - 35
D
40 - 45
D
50 - 55
POL2
Data register
POL
Latch
V
DD2
Level shifter
V
SS2
V
0
to
V
9
D/A converter
Voltage follower output
LPC
S
1
S
2
S
3
S
384
2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER
S
1
S
2
S
383
S
384
V
0
•
•
•
•
•
5
Multi-
plexer
5
6-bit D/A converter
V
4
V
5
•
•
•
•
•
V
9
POL
2
µ
PD16715
3. PIN CONFIGURATION (
µ
PD16715N-
× × ×
)
V
SS2
V
DD2
R/L
POL
STB
D
55
D
54
D
53
D
52
D
51
D
50
D
45
D
44
D
43
D
42
D
41
D
40
D
35
D
34
D
33
D
32
D
31
D
30
STHL
V
9
V
8
V
7
V
6
V
5
V
4
V
3
V
2
V
1
V
0
V
DD1
CLK
V
SS1
POL2
STHR
D
25
D
24
D
23
D
22
D
21
D
20
D
15
D
14
D
13
D
12
D
11
D
10
D
05
D
04
D
03
D
02
D
01
D
00
LPC
TEST
V
DD2
V
SS2
S
384
S
383
S
382
Copper Foll
suface
S
3
S
2
S
1
This figure does not specify the TCP package.
3
µ
PD16715
4. PIN FUNCTIONS
Pin Symbol
S
1
to S
384
D
00
to D
05
D
10
to D
15
D
20
to D
25
D
30
to D
35
D
40
to D
45
D
50
to D
55
R/L
Pin Name
Driver output
Display data input
Description
The D/A converted 64-gray-scale analog voltage is output.
The display data is input with a width of 36 bits, viz.; the gray scale data (6 bits) by
6 dots (2 pixels).
DX0: LSB, DX5: MSB
Shift direction control input
STHR
STHL
CLK
Right shift start
pulse input/output
Left shift start
pulse input/output
Shift clock input
STB
Latch input
POL
Polarity input
POL2
LPC
Data inversion
Low power control
input
V
0
to V
9
γ
-corrected power
supplies
TEST
V
DD1
V
DD2
V
SS1
V
SS2
Test pin
Logic power supply
Driver power supply
Logic ground
Driver ground
These refer to the start pulse input/output pins when driver ICs are connected in
cascade. The shift directions of the shift registers are as follows.
R/L = H : STHR input, S
1
→
S
384
, STHL output
R/L = L : STHL input, S
384
→
S
1
, STHR output
R/L = H : Becomes the start pulse input pin.
R/L = L : Becomes the start pulse output pin.
R/L = H : Becomes the start pulse output pin.
R/L = L : Becomes the start pulse input pin.
Refers to the shift register’s shift clock input. The display data is incorporated into
the data register at the rising edge. At the rising edge of the 64th clock after the
start pulse input, the start pulse output reaches the high level, thus becoming the
start pulse of the next-level driver. The initial-level driver’s 64th clock becomes
valid as the next-level driver’s start pulse is input. If 66 clock pulses are input
after input of the start pulse, input of display data is halted automatically. The
contents of the shift register are cleared at the STB’s rising edge.
The contents of the data register are transferred to the latch circuit at the rising
edge. And, at the falling edge, the gray scale voltage is supplied to the driver. It is
necessary to ensure input of one pulse per horizontal period.
POL = L; The S
2n-1
output uses V
0
to V
4
as the reference supply;
The S
2n
output uses V
5
to V
9
as the reference supply.
POL = H; The S
2n-1
output uses V
5
to V
9
as the reference supply;
The S
2n
output uses V
0
to V
4
as the reference supply.
POL2 = H : Display data is inverted.
POL2 = L : Display data is not inverted.
The output buffer constant current source is blocked, reducing current
consumption. In lower power mode (LPC = ‘H’: DC-level input possible), the
ordinary static current consumption can be reduced by approx. 20%. The
condition that low power mode can be used is that the load constant is at least 5
kW + 100 pF.
Input the
γ-corrected
power supplies from outside by using operational amplifier.
Make sure to maintain the following relationships. During the gray scale voltage
output, be sure to keep the gray scale level power supply at a constant level.
V
DD2
> V
0
> V
1
> V
2
> V
3
> V
4
> V
5
> V
6
> V
7
> V
8
> V
9
> V
SS2
TEST
=
H or Open : Standard mode.
TEST
=
L : Test mode. Please input ‘‘H’’ level.
3.3 V
±0.3
V
9.0 V to 13.5 V
Grounding
Grounding
5. CAUTIONS
(1) The power start sequence must be V
DD1
, logic input, and V
DD2
& V
0
to V
9
in that order. Reverse this
sequence to shut down. (Simultaneous power application to V
DD2
and V
0
to V
9
is possible.)
(2) To stabilize the supply voltage, please be sure to insert a 0.47
µ
F bypass capacitor between V
DD1
-V
SS1
and V
DD2
-V
SS2
. Furthermore, for increased precision of the D/A converter, insertion of a bypass
capacitor of about 0.01
µ
F is also advised between the
γ
-corrected power supply terminals (V
0
, V
1
,
V
2
,···, V
9
) and V
SS2
.
4
µ
PD16715
6. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE
This product incorporates a 6-bit D/A converter whose odd output pins and even output pins output respectively
gray scale voltages of differing polarity with respect to the LCD’s counter electrode (common electrode) voltage.
The D/A converter consists of ladder resistors and switches. The ladder resistors r
0
to r
62
are so designed that the
ratios between the LCD panel’s
γ
-corrected voltages and V
0
’ to V
63
’ and V
0
’’ to V
63
’’ are roughly equal; and their
respective resistance values are as shown on page 6. Among the 5-by-2
γ
-corrected voltages, input gray scale
voltages of the same polarity with respect to the common voltage, for the respective five
γ
-corrected voltages of V
0
to V
4
and V
5
to V
9
. If fine gray-scale voltage precision is not necessary, the voltage follower crcuit supplied to the
γ
-
corrected power supplies V
1
to V
4
and V
11
to V
16
can be deleted.
Figure 1 shows the relationship between the driving voltages such as liquid-crystal driving voltages V
DD2
and V
SS2
,
common electrode potential V
COM
, and
γ
-corrected voltages V
0
to V
9
and the input data. Be sure to maintain the
voltage relationships of V
DD2
> V
0
> V
1
> V
2
> V
3
> V
4
> V
5
> V
6
> V
7
> V
8
> V
9
> V
SS2
. Figures 2-1 and 2-2 show the
relationship between the input data and the output data. Table 1 shows the resistance values of the resistor strings.
This driver IC is designed for single-sided mounting. Therefore, please do not use it for
γ
-corrected power supply
level inversion in double-sided mounting. Because the current flowing through ladder resistors r
0
to r
62
is small, its
use for double-sided mounting impairs the IC’s stable operation when the level of the
γ
-corrected power supply
terminal is inverted thus causing display failures.
Figure 1. Relationship between Input Data and Output Voltage
0.2 V
V
DD2
V
0
8
V
1
24
V
2
24
V
3
7
V
4
V
COM
V
5
7
V
6
24
V
7
24
V
8
8
V
9
0.2 V
V
SS2
00
08
10
18
20
28
30
38
3F
Split interval
Input data (HEX)
5
51单片机
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