HD74AC112/HD74ACT112
Dual JK Negative Edge-Triggered Flip-Flop
Description
The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to
each flip-flop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level
of the J and K inputs may change when the clock is High and the bistable will perform according to the
Truth Table as long as minimum setup and hold times are observed. Input data is transferred to the outputs
on the falling edge of the clock pulse.
Features
•
Outputs Source/Sink 24 mA
•
HD74ACT112 has TTL-Compatible Inputs
Pin Arrangement
CP
1
1
K
1
2
J
1
3
S
D1
4
Q
1
5
Q
1
6
Q
2
7
GND 8
(Top view)
16 V
CC
15
C
D1
14
C
D2
13
CP
2
12 K
2
11 J
2
10
S
D2
9 Q
2
HD74AC112/HD74ACT112
Logic Symbol
4
S
D1
J
1
CP
1
K
1
Q
1
Q
1
5
10
S
D2
J
2
CP
2
K
2
Q
2
7
Q
2
9
3
1
2
11
13
6 12
C
D1
15
C
D2
14
V
CC
= Pin16
GND = Pin8
Pin Names
J
1
, J
2
, K
1
, K
2
CP
1
,
CP
2
C
D1
,
C
D2
S
D1
,
S
D2
Q
1
, Q
2
,
Q
1
,
Q
2
Data Inputs
Clock Pulse Inputs (Active Falling Edge)
Direct Clear Inputs (Active Low)
Direct Set Inputs (Active Low)
Outputs
Asynchronous Inputs:
Low input to
S
D
sets Q to High level
Low input to
C
D
sets Q to Low level
Clear and Set are independent of clock
Simultaneous Low on
C
D
and
S
D
makes both Q and
Q
High
2
HD74AC112/HD74ACT112
Truth Table
Inputs
@t
n
J
L
L
H
H
t
n
t
n + 1
H
L
:
:
:
:
K
L
H
L
H
Bit time before clock pulse.
Bit time after clock pulse.
High Voltage Level
Low Voltage Level
Outputs
@t
n + 1
Q
Qn
L
H
Qn
Logic Diagram
S
D
C
D
J
K
#
CP
CP
#
CP
#
CP
CP
CP
CP
#CP
Q
CP
CP
#
CP
Q
DC Characteristics
(unless otherwise specified)
Item
Maximum quiescent supply current
Maximum quiescent supply current
Maximum additional I
CC
/input
(HD74ACT112)
Symbol
I
CC
I
CC
I
CCT
Max
80
8.0
1.5
Unit
µA
µA
mA
Condition
V
IN
= V
CC
or ground, V
CC
= 5.5 V,
Ta = Worst case
V
IN
= V
CC
or ground, V
CC
= 5.5 V,
Ta = 25°C
V
IN
= V
CC
– 2.1 V, V
CC
= 5.5 V
Ta = Worst case
3
HD74AC112/HD74ACT112
AC Characteristics: HD74AC112
Ta = +25°C
C
L
= 50 pF
Item
Maximum clock
frequency
Propagation delay
C
P
to Q or
Q
Propagation delay
C
P
to Q or
Q
Propagation delay
C
D
,
S
D
to Q or
Q
Propagation delay
C
D
,
S
D
to Q or
Q
Note:
t
PHL
t
PLH
t
PHL
t
PLH
Symbol
f
max
V
CC
(V)*
1
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
Min
125
150
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Typ
—
—
11.0
8.5
11.0
8.5
9.5
7.0
11.5
9.0
Max
—
—
14.0
11.0
14.0
11.0
12.5
9.5
14.5
11.0
Ta = –40°C to +85°C
C
L
= 50 pF
Min
100
125
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max
—
—
15.0
12.0
15.0
12.0
13.5
10.5
15.5
12.5
ns
Unit
MHz
1. Voltage Range 3.3 is 3.3 V
±
0.3 V
Voltage Range 5.0 is 5.0 V
±
0.5 V
AC Operating Requirements: HD74AC112
Ta = +25°C
C
L
= 50 pF
Item
Setup time
J or K to
C
P
Hold time
C
P
to J or K
Pulse width
C
P
or
C
D
or
S
D
Recovery time
C
D
or
S
D
to
C
P
Note:
t
rec
t
w
t
h
Symbol
t
su
V
CC
(V)*
1
Typ
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.0
2.0
–1.5
–0.5
2.0
2.0
–1.0
–1.0
Ta = –40°C
to +85°C
C
L
= 50 pF
Guaranteed Minimum
5.5
4.5
0.0
0.0
5.5
4.5
3.5
3.0
6.0
4.6
0.0
0.0
7.0
5.0
3.5
3.0
Unit
ns
1. Voltage Range 3.3 is 3.3 V
±
0.3 V
Voltage Range 5.0 is 5.0 V
±
0.5 V
4
HD74AC112/HD74ACT112
AC Characteristics: HD74ACT112
Ta = +25°C
C
L
= 50 pF
Item
Maximum clock
frequency
Propagation delay
C
P
to Q or
Q
Propagation delay
C
P
to Q or
Q
Propagation delay
C
D
,
S
D
to Q or
Q
Propagation delay
C
D
,
S
D
to Q or
Q
Note:
Symbol
f
max
t
PLH
t
PHL
t
PLH
t
PHL
V
CC
(V)*
1
5.0
5.0
5.0
5.0
5.0
Min
100
1.0
1.0
1.0
1.0
Typ
—
10.5
10.5
8.0
10.5
Max
—
13.0
13.0
10.0
12.5
Ta = –40°C to +85°C
C
L
= 50 pF
Min
80
1.0
1.0
1.0
1.0
Max
—
14.0
14.0
11.0
13.5
Unit
MHz
ns
1. Voltage Range 5.0 is 5.0 V
±
0.5 V
AC Operating Requirements: HD74ACT112
Ta = +25°C
C
L
= 50 pF
Item
Setup time
J or K to
C
P
Hold time
C
P
to J or K
Pulse width
C
P
or
C
D
or
S
D
Recovery time
C
D
,
S
D
to
C
P
Note:
Symbol
t
su
t
h
t
w
t
rec
V
CC
(V)*
1
Typ
5.0
5.0
5.0
5.0
2.5
0.0
4.5
–2.5
Ta = –40°C
to +85°C
C
L
= 50 pF
Guaranteed Minimum
7.0
1.5
7.0
3.0
8.0
1.5
8.0
3.0
Unit
ns
1. Voltage Range 5.0 is 5.0 V
±
0.5 V
Capacitance
Item
Input capacitance
Power dissipation capacitance
Symbol
C
IN
C
PD
Typ
4.5
35.0
Unit
pF
pF
Condition
V
CC
= 5.5 V
V
CC
= 5.0 V
5
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