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HD74ACT112FP: 产品描述J-K Flip-Flop, ACT Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, FP-16DA; 产品类别逻辑逻辑; 文件大小56KB，共8页; 制造商Hitachi （Renesas ）; 官网地址http://www.renesas.com/eng/

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HD74ACT112FP概述

J-K Flip-Flop, ACT Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, FP-16DA

HD74ACT112FP规格参数

参数名称	属性值
零件包装代码	SOIC
包装说明	SOP, SOP16,.3
针数	16
Reach Compliance Code	unknown
系列	ACT
JESD-30 代码	R-PDSO-G16
长度	10.06 mm
负载电容（CL）	50 pF
逻辑集成电路类型	J-K FLIP-FLOP
最大频率@ Nom-Sup	80000000 Hz
位数	2
功能数量	2
端子数量	16
最高工作温度	85 °C
最低工作温度	-40 °C
输出极性	COMPLEMENTARY
封装主体材料	PLASTIC/EPOXY
封装代码	SOP
封装等效代码	SOP16,.3
封装形状	RECTANGULAR
封装形式	SMALL OUTLINE
电源	5 V
传播延迟（tpd）	14 ns
认证状态	Not Qualified
座面最大高度	2.2 mm
最大供电电压 (Vsup)	5.5 V
最小供电电压 (Vsup)	4.5 V
标称供电电压 (Vsup)	5 V
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子形式	GULL WING
端子节距	1.27 mm
端子位置	DUAL
触发器类型	NEGATIVE EDGE
宽度	5.5 mm
最小 fmax	80 MHz
Base Number Matches	1

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HD74AC112/HD74ACT112

Dual JK Negative Edge-Triggered Flip-Flop

ADE-205-364 (Z)

1st. Edition

Sep. 2000

Description

The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to

each flip-flop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level

of the J and K inputs may change when the clock is High and the bistable will perform according to the

Truth Table as long as minimum setup and hold times are observed. Input data is transferred to the outputs

on the falling edge of the clock pulse.

Features

•

Outputs Source/Sink 24 mA

•

HD74ACT112 has TTL-Compatible Inputs

Pin Arrangement

GND 8

(Top view)

16 V

12 K

11 J

9 Q

HD74ACT112FP相似产品对比

	HD74ACT112FP	HD74ACT112P	HD74ACT112RP	HD74ACT112T	HD74AC112P
描述	J-K Flip-Flop, ACT Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, FP-16DA	J-K Flip-Flop, ACT Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDIP16, DP-16	J-K Flip-Flop, ACT Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, FP-16DN	J-K Flip-Flop, ACT Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, TTP-16DA	J-K Flip-Flop, AC Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDIP16, DP-16
零件包装代码	SOIC	DIP	SOIC	SOIC	DIP
包装说明	SOP, SOP16,.3	DIP, DIP16,.3	SOP, SOP16,.25	TSSOP, TSSOP16,.25	DIP, DIP16,.3
针数	16	16	16	16	16
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown
系列	ACT	ACT	ACT	ACT	AC
JESD-30 代码	R-PDSO-G16	R-PDIP-T16	R-PDSO-G16	R-PDSO-G16	R-PDIP-T16
长度	10.06 mm	19.2 mm	9.9 mm	5 mm	19.2 mm
负载电容（CL）	50 pF	50 pF	50 pF	50 pF	50 pF
逻辑集成电路类型	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP
最大频率@ Nom-Sup	80000000 Hz	80000000 Hz	80000000 Hz	80000000 Hz	100000000 Hz
位数	2	2	2	2	2
功能数量	2	2	2	2	2
端子数量	16	16	16	16	16
最高工作温度	85 °C	85 °C	85 °C	85 °C	85 °C
最低工作温度	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
输出极性	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	SOP	DIP	SOP	TSSOP	DIP
封装等效代码	SOP16,.3	DIP16,.3	SOP16,.25	TSSOP16,.25	DIP16,.3
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	SMALL OUTLINE	IN-LINE	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	IN-LINE
电源	5 V	5 V	5 V	5 V	3.3/5 V
传播延迟（tpd）	14 ns	14 ns	14 ns	14 ns	15 ns
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	2.2 mm	5.06 mm	1.75 mm	1.1 mm	5.06 mm
最大供电电压 (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	3.6 V
最小供电电压 (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V	3 V
标称供电电压 (Vsup)	5 V	5 V	5 V	5 V	3.3 V
表面贴装	YES	NO	YES	YES	NO
技术	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
端子形式	GULL WING	THROUGH-HOLE	GULL WING	GULL WING	THROUGH-HOLE
端子节距	1.27 mm	2.54 mm	1.27 mm	0.65 mm	2.54 mm
端子位置	DUAL	DUAL	DUAL	DUAL	DUAL
触发器类型	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE
宽度	5.5 mm	7.62 mm	3.95 mm	4.4 mm	7.62 mm
最小 fmax	80 MHz	80 MHz	80 MHz	80 MHz	125 MHz
Base Number Matches	1	1	1	1	-
是否Rohs认证	-	不符合	-	不符合	不符合
JESD-609代码	-	e0	-	e0	e0
端子面层	-	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)

HD74ACT112FP

HD74ACT112FP概述

HD74ACT112FP规格参数

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HD74ACT112FP相似产品对比

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