TS68C000
Low Power HCMOS 16-/32-bit
Hi-Rel Microprocessor
Datasheet
Features
•
•
•
•
•
•
•
•
•
16-/32-bit Data and Address Register
16-Mbyte Direct Addressing Range
56 Powerful Instruction Types
Operations on Five Main Data Types
Memory Mapped Input/Output
14 Addressing Modes
Three Available Versions: 8 MHz/10 MHz and 12.5 MHz
Military Temperature Range: -55/+125°C
Power Supply: 5V
DC
± 10%
Description
The TS68C000 reduced power consumption device dissipates an order of magnitude less power than the HMOS TS68000.
The TS68C000 is an implementation of the TS68000 16/32 microprocessor architecture. The TS68C000 has a 16-bit data
bus and 24-bit address bus while the full architecture provides for 32-bit address and data-buses. It is completely code-
compatible with the HMOS TS68000, TS68008 8-bit data bus implementation of the TS68000 and the TS68020 32-bit
implementation of the architecture. Any user-mode programs written using the TS68C000 instruction set will run
unchanged on the TS68000, TS68008 and TS68020. This is possible because the user programming model is identical for
all processors and the instruction sets are proper sub-sets of the complete architecture.
Screening/Quality
This product is manufactured in full compliance with:
•
MIL-STD-883 class B
•
DESC drawing 5962-89462
•
e2v standards
C Suffix
DIL 64
Ceramic Package
F Suffix
CQFP 68
Ceramic Quad Flat Pack (on reque
E Suffix
LCCC 68
Leadless Ceramic Chip Carrier
R Suffix
PGA 68
Pin Grid Array
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for the latest version of the datasheet
e2v semiconductors SAS 2007
0853B–HIREL–09/07
TS68C000
1. General Description
1.1
Introduction
This detail specification contains both a summary of the TS68C000 as well as detailed set of paramet-
rics. The purpose is twofold to provide an instruction to the TS68C000 and support for the sophisticated
user. For detail information on the TS68C000, refer to "68000 16-bit microprocessor user’s manual".
1.2
Detailed Block Diagram
The functional block diagram is given in
Figure 1-1
below.
Figure 1-1.
Status
and
Control
Clock
Block Diagram
Clock Gen.
and
Timing Control
Interrupt
Control
Instruction
Decode
Bus
Control
Logic
VCC
VGND
Control
Store
M Store
N Store
Alu Function
and Reg
Selection
System
Control
Signals
Internal
Control
bus
Instruction
Register
DATA BUS
Data
Bus
Buffer
16-bit
Data
Bus
Address High
Execution Unit
and Registers
16-bit
Alu
Address Low
Execution Unit
and Registers
16-bit
Alu
Data Execution
Unit
and Registers
16-bit
Alu
Addr.
Bus
Buffer
32-bit
Address
Bus
ADDRESS BUS
2
0853B–HIREL–09/07
e2v semiconductors SAS 2007
TS68C000
Figure 1-5.
68-ceramic Quad Flat Pack
Index
68
1
R/W
LDS
LDS
AS
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
52
51
DTACK
BG
BGACK
BR
VCC
CLK
GND
GND
NC
HALT
RESET
VMA
E
VPA
BERR
IPL2
IPL1
TOP VIEW
17
18
34
IPL0
FC2
FC1
FC0
NC
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
D13
D14
D15
GND
GND
A23
A22
A21
VCC
A20
A19
A18
A17
A16
A15
A14
A13
35
1.4
Terminal Designations
The function, category and relevant symbol of each terminal of the device are given in the following
table.
Table 1-1.
Symbol
V
CC
V
SS(1)
FC0 to FC2
IPL0 to IPL2
A1 to A23
AS
R/W
Outputs
UDS
LDS
DTACK
BR
Inputs
BGACK
BG
Bus arbitration control
Output
Input
Asynchronous bus control
Terminal Designations
Function
Power supply (2 terminals)
Power supply (2 terminals)
Processor status
Interrupt control
Address bus
Category
Supply
Terminals
Outputs
Inputs
Outputs
5
0853B–HIREL–09/07
e2v semiconductors SAS 2007
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